PIC18F65K90-I/MRRSL Microchip Technology, PIC18F65K90-I/MRRSL Datasheet - Page 59
![MCU PIC 32K FLASH MEM XLP 64QFN](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F65K90-I/MRRSL
Manufacturer Part Number
PIC18F65K90-I/MRRSL
Description
MCU PIC 32K FLASH MEM XLP 64QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Specifications of PIC18F65K90-I/MRRSL
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Core Processor
PIC
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
53
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Controller Family/series
PIC18
Eeprom Memory Size
1024Byte
Ram Memory Size
2048Byte
Cpu Speed
16MIPS
No. Of Timers
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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REGISTER 4-1:
2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
CCP10MD
R/W-0
Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K90).
(1)
CCP10MD: PMD CCP10 Enable/Disable bit
1 = Peripheral Module Disable (PMD) is enabled for CCP10, disabling all of its clock sources
0 = PMD is disabled for CCP10
CCP9MD: PMD CCP9 Enable/Disable bit
1 = Peripheral Module Disable (PMD) is enabled for CCP9, disabling all of its clock sources
0 = PMD is disabled for CCP9
CCP8MD: PMD CCP8 Enable/Disable bit
1 = Peripheral Module Disable (PMD) is enabled for CCP8, disabling all of its clock sources
0 = PMD is disabled for CCP8
CCP7MD: PMD CCP7 Enable/Disable bit
1 = Peripheral Module Disable (PMD) is enabled for CCP7, disabling all of its clock sources
0 = PMD is disabled for CCP7
CCP6MD: PMD CCP6 Enable/Disable bit
1 = Peripheral Module Disable (PMD) is enabled for CCP6, disabling all of its clock sources
0 = PMD is disabled for CCP6
CCP5MD: PMD CCP5 Enable/Disable bit
1 = Peripheral Module Disable (PMD) is enabled for CCP5, disabling all of its clock sources
0 = PMD is disabled for CCP5
CCP4MD: PMD CCP4 Enable/Disable bit
1 = Peripheral Module Disable (PMD) is enabled for CCP4, disabling all of its clock sources
0 = PMD is disabled for CCP4
TMR12MD: TMR12MD Disable bit
1 = PMD is enabled and all TMR12MD clock sources are disabled
0 = PMD is disabled and TMR12MD is enabled
CCP9MD
R/W-0
PMD3: PERIPHERAL MODULE DISABLE REGISTER 3
(1)
W = Writable bit
‘1’ = Bit is set
CCP8MD
R/W-0
CCP7MD
R/W-0
Preliminary
(1)
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PIC18F87K90 FAMILY
(1)
CCP6MD
R/W-0
CCP5MD
R/W-0
x = Bit is unknown
CCP4MD
R/W-0
DS39957B-page 59
TMR12MD
R/W-0
bit 0
(1)
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