PIC18F65K90-I/MRRSL Microchip Technology, PIC18F65K90-I/MRRSL Datasheet - Page 459
![MCU PIC 32K FLASH MEM XLP 64QFN](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F65K90-I/MRRSL
Manufacturer Part Number
PIC18F65K90-I/MRRSL
Description
MCU PIC 32K FLASH MEM XLP 64QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Specifications of PIC18F65K90-I/MRRSL
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Core Processor
PIC
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
53
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Controller Family/series
PIC18
Eeprom Memory Size
1024Byte
Ram Memory Size
2048Byte
Cpu Speed
16MIPS
No. Of Timers
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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BNC
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
2010 Microchip Technology Inc.
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
No
PC
If Carry
If Carry
Q1
Q1
PC
PC
Read literal
Read literal
operation
Branch if Not Carry
BNC
-128 n 127
if Carry bit is ‘ 0 ’,
(PC) + 2 + 2n PC
None
If the Carry bit is ‘ 0 ’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
1(2)
HERE
1110
No
Q2
‘n’
Q2
‘n’
=
=
=
=
=
n
address (HERE)
0 ;
address (Jump)
1 ;
address (HERE + 2)
0011
BNC
operation
Process
Process
Data
Data
No
Q3
Q3
Jump
nnnn
operation
operation
Write to
PC
No
No
Q4
Q4
nnnn
Preliminary
PIC18F87K90 FAMILY
BNN
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
No
PC
If Negative
If Negative
Q1
Q1
PC
PC
Read literal
Read literal
operation
Branch if Not Negative
BNN
-128 n 127
if Negative bit is ‘ 0 ’,
(PC) + 2 + 2n PC
None
If the Negative bit is ‘ 0 ’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
1(2)
HERE
1110
No
Q2
‘n’
Q2
‘n’
=
=
=
=
=
n
address (HERE)
0 ;
address (Jump)
1 ;
address (HERE + 2)
0111
BNN
operation
Process
Process
Data
Data
No
Q3
Q3
DS39957B-page 459
Jump
nnnn
operation
operation
Write to
PC
No
No
Q4
Q4
nnnn
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