PIC18F65K90-I/MRRSL Microchip Technology, PIC18F65K90-I/MRRSL Datasheet - Page 30
![MCU PIC 32K FLASH MEM XLP 64QFN](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F65K90-I/MRRSL
Manufacturer Part Number
PIC18F65K90-I/MRRSL
Description
MCU PIC 32K FLASH MEM XLP 64QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Specifications of PIC18F65K90-I/MRRSL
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Core Processor
PIC
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
53
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Controller Family/series
PIC18
Eeprom Memory Size
1024Byte
Ram Memory Size
2048Byte
Cpu Speed
16MIPS
No. Of Timers
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC18F87K90 FAMILY
TABLE 1-4:
DS39957B-page 30
RG0/ECCP3/P3A
RG1/TX2/CK2/AN19/
C3OUT
RG2/RX2/DT2/AN18/
C3INA
RG3/CCP4/AN17/P3D/
C3INB
RG4/SEG26/RTCC/
T7CKI/T5G/CCP5/AN16/
P1D/C3INC
RG5
Legend: TTL = TTL compatible input
Note 1:
RG0
ECCP3
P3A
RG1
TX2
CK2
AN19
C3OUT
RG2
RX2
DT2
AN18
C3INA
RG3
CCP4
AN17
P3D
C3INB
RG4
SEG26
RTCC
T7CKI
T5G
CCP5
AN16
P1D
C3INC
2:
3:
4:
Pin Name
(3)
ST
I
P
I
Default assignment for ECCP2 when the CCP2MX Configuration bit is set.
Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared.
Not available on PIC18F65K90 and PIC18F85K90 devices.
The CCP6, CCP7, CCP8 and CCP9 pin placement depends on the ECCPMX Configuration bit setting.
2
C™ = I
= Schmitt Trigger input with CMOS levels
= Input
= Power
PIC18F8XK90 PINOUT I/O DESCRIPTIONS (CONTINUED)
2
C/SMBus
Pin Number
TQFP
10
5
6
7
8
9
Type
Pin
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Buffer
Type
Preliminary
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
—
—
—
—
—
—
PORTG is a bidirectional I/O port.
See the MCLR/RG5 pin.
Digital I/O.
Capture 3 input/Compare 3 output/PWM3 output.
ECCP3 PWM Output A.
Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see related RX2/DT2).
Analog Input 19.
Comparator 3 output.
Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see related TX2/CK2).
Analog Input 18.
Comparator 3 Input A.
Digital I/O.
Capture 4 input/Compare 4 output/PWM4 output.
Analog Input 17.
ECCP3 PWM Output D.
Comparator 3 Input B.
Digital I/O.
SEG26 output for LCD.
RTCC output.
Timer7 clock input.
Timer5 external clock gate input.
Capture 5 input/Compare 5 output/PWM5 output.
Analog Input 16.
ECCP1 PWM Output D.
Comparator 3 Input C.
CMOS = CMOS compatible input or output
Analog = Analog input
O
OD
= Output
= Open-Drain (no P diode to V
Description
2010 Microchip Technology Inc.
DD
)
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