PIC18F27J13-I/ML Microchip Technology, PIC18F27J13-I/ML Datasheet - Page 553

• Manufacturer Part Number: PIC18F27J13-I/ML
• Description: IC PIC MCU 128KB FLASH 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J13-I/ML

• Core Size: 8-Bit
• Program Memory Size: 128KB (64K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Controller Family/series: PIC18
• Cpu Speed: 48MHz
• Digital Ic Case Style: QFN
• Supply Voltage Range: 1.8V To 5.5V
• Embedded Interface Type: I2C, SPI, USART
• Rohs Compliant: Yes
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, EUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 19
• Number Of Timers: 8
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DM164128, DM180021, DM183026-2, DV164131, MA180030, DM183022, DM183032, DV164136, MA180024
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 10 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180030 - BOARD DEMO PIC18F47J13 FS USBMA180029 - BOARD DEMO PIC18F47J53 FS USB
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

 2010 Microchip Technology Inc.
High/Low-Voltage Detect Characteristics ................ 505
High-Voltage Detect (VDIRMAG = 1) ....................... 395
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Low-Voltage Detect (VDIRMAG = 0) ....................... 394
MSSPx I
MSSPx I
Parallel Master Port Read ........................................ 515
Parallel Master Port Write ........................................ 516
Parallel Slave Port Read .................................. 189, 191
Parallel Slave Port Write .................................. 189, 192
PWM Auto-Shutdown with Auto-Restart Enabled .... 284
PWM Auto-Shutdown with Firmware Restart ........... 284
PWM Direction Change ........................................... 281
PWM Direction Change at Near 100%
PWM Output ............................................................ 266
Read and Write, 8-Bit Data, Demultiplexed
Read, 16-Bit Data, Demultiplexed Address ............. 199
Read, 16-Bit Multiplexed Data, Fully Multiplexed
Read, 16-Bit Multiplexed Data, Partially
Read, 8-Bit Data, Fully Multiplexed
Read, 8-Bit Data, Partially Multiplexed Address ...... 196
Read, 8-Bit Data, Partially Multiplexed
Read, 8-Bit Data, Wait States Enabled,
Repeated Start Condition ......................................... 334
Reset, Watchdog Timer (WDT), Oscillator Start-up
Send Break Character Sequence ............................ 360
Slave Synchronization ............................................. 298
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ......................................... 297
SPI Mode (Slave Mode, CKE = 0) ........................... 299
SPI Mode (Slave Mode, CKE = 1) ........................... 299
Steering Event at Beginning of Instruction
Steering Event at End of Instruction
Synchronous Reception (Master Mode, SREN) ...... 363
Synchronous Transmission ...................................... 361
Synchronous Transmission (Through TXEN) .......... 362
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2C Bus Data .......................................................... 522
C Acknowledge Sequence .................................... 338
C Bus Start/Stop Bits ............................................. 522
C Master Mode (7 or 10-Bit Transmission) ............ 336
C Master Mode (7-Bit Reception) .......................... 337
C Slave Mode (10-Bit Reception,
C Slave Mode (10-Bit Reception, SEN = 0) .......... 323
C Slave Mode (10-Bit Reception, SEN = 1) .......... 328
C Slave Mode (10-Bit Transmission) ..................... 324
C Slave Mode (7-Bit Reception,
C Slave Mode (7-Bit Reception, SEN = 0) ............ 319
C Slave Mode (7-Bit Reception, SEN = 1) ............ 327
C Slave Mode (7-Bit Transmission) ....................... 321
C Slave Mode General Call Address
C Stop Condition Receive or Transmit Mode ........ 338
SEN = 0, ADMSK = 01001) ............................. 322
SEN = 0, ADMSK = 01011) ............................. 320
Sequence (7 or 10-Bit Addressing Mode) ........ 329
Duty Cycle ........................................................ 282
Address ............................................................ 196
16-Bit Address ................................................. 200
Multiplexed Address ......................................... 199
16-Bit Address ................................................. 198
Address, Enable Strobe ................................... 197
Partially Multiplexed Address ........................... 196
Timer (OST) and Power-up Timer (PWRT) ..... 511
V
(STRSYNC = 1) ............................................... 288
(STRSYNC = 0) ............................................... 288
DD
2
2
C Bus Data ............................................... 524
C Bus Start/Stop Bits ................................ 524
Rise > T
PWRT
) ............................................ 69
DD
,
Preliminary
PIC18F47J13 FAMILY
Timing Diagrams and Specifications
Time-out Sequence on Power-up (MCLR Not
Time-out Sequence on Power-up (MCLR Not
Time-out Sequence on Power-up (MCLR
Timer Pulse Generation ........................................... 254
Timer0 and Timer1 External Clock .......................... 512
Timer1 Gate Count Enable Mode ............................ 215
Timer1 Gate Single Pulse Mode .............................. 217
Timer1 Gate Single Pulse/Toggle
Timer1 Gate Toggle Mode ....................................... 216
Timer3/5 Gate Count Enable Mode ......................... 226
Timer3/5 Gate Single Pulse Mode ........................... 228
Timer3/5 Gate Single Pulse/Toggle
Timer3/5 Gate Toggle Mode .................................... 227
Transition for Entry to Idle Mode ................................ 53
Transition for Entry to SEC_RUN Mode .................... 49
Transition for Entry to Sleep Mode ............................ 51
Transition for Two-Speed Start-up
Transition for Wake From Idle to Run Mode .............. 53
Transition for Wake From Sleep (HSPLL) ................. 51
Transition From RC_RUN Mode to
Transition From SEC_RUN Mode to
Transition to RC_RUN Mode ..................................... 50
Write, 16-Bit Data, Demultiplexed Address ............. 199
Write, 16-Bit Multiplexed Data, Fully
Write, 16-Bit Multiplexed Data, Partially
Write, 8-Bit Data, Fully Multiplexed
Write, 8-Bit Data, Partially Multiplexed Address ...... 197
Write, 8-Bit Data, Partially Multiplexed
Write, 8-Bit Data, Wait States Enabled,
4x PLL Clock ........................................................... 509
96 MHz PLL Clock ................................................... 509
CLKO and I/O Requirements ................................... 510
Enhanced Capture/Compare/PWM
EUSARTx Synchronous Receive Requirements ..... 526
EUSARTx Synchronous Transmission
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Slave Mode
External Clock Requirements .................................. 508
I
I
Internal RC Accuracy (INTOSC and
2
2
C Bus Data Requirements (Slave Mode) .............. 523
C Bus Start/Stop Bits Requirements
Tied to V
Tied to V
Tied to V
Combined Mode .............................................. 218
Combined Mode .............................................. 229
(INTRC to HSPLL) ........................................... 428
PRI_RUN Mode ................................................. 50
PRI_RUN Mode (HSPLL) .................................. 49
Multiplexed 16-Bit Address .............................. 200
Multiplexed Address ........................................ 200
16-Bit Address ................................................. 198
Address, Enable Strobe ................................... 198
Partially Multiplexed Address .......................... 197
Requirements .................................................. 514
Requirements .................................................. 526
(Master Mode, CKE = 0) .................................. 518
(Master Mode, CKE = 1) .................................. 519
(Slave Mode, CKE = 0) .................................... 520
Requirements (CKE = 1) ................................. 521
(Slave Mode) ................................................... 522
INTRC Sources) .............................................. 509
DD
DD
DD
), Case 1 ......................................... 69
), Case 2 ......................................... 69
, V
DD
Rise < T
PWRT
DS39974A-page 553
) ....................... 68