AT32UC3L064-AUT Atmel, AT32UC3L064-AUT Datasheet - Page 64
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AT32UC3L064-AUT
Manufacturer Part Number
AT32UC3L064-AUT
Description
MCU AVR32 64KB FLASH 48TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.AT32UC3L-EK.pdf
(858 pages)
3.AT32UC3L016-D3HT.pdf
(110 pages)
Specifications of AT32UC3L064-AUT
Core Processor
AVR
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TQFP, 48-VQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
SPI/TWI/USART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
36
Number Of Timers
7
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
AT32UC3L-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
9-ch x 10-bit
Package
48TQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
50 MHz
Operating Supply Voltage
1.8|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3L064-AUT
Manufacturer:
HONGFA
Quantity:
30 000
Part Number:
AT32UC3L064-AUT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
7.10.3
7.10.3.1
Table 7-38.
Notes:
32099F–11/2010
Symbol
USPI0
USPI1
USPI2
USPI3
USPI4
USPI5
1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
2. Where:
USART in SPI Mode Timing
cess technology. These values are not covered by test limits in production.
Master mode
USART in SPI Mode Timing, Master Mode
Parameter
MISO setup time before SPCK rises
MISO hold time after SPCK rises
SPCK rising to MOSI delay
MISO setup time before SPCK falls
MISO hold time after SPCK falls
SPCK falling to MOSI delay
t
SAMPLE
Figure 7-8.
Figure 7-9.
=
SPCK
SPCK
MISO
MOSI
MISO
MOSI
t
SPCK
–
⎛
⎝
------------------------------------
2
×
USART in SPI Master Mode With (CPOL= CPHA= 0) or (CPOL= CPHA= 1)
USART in SPI Master Mode With (CPOL= 0 and CPHA= 1) or (CPOL= 1 and
CPHA= 0)
t
t
CLKUSART
SPCK
USPI2
USPI5
1
-- -
2
⎞
⎠
×
(1)
t
CLKUSART
USPI0
USPI3
3.0V to 3.6V,
Conditions
V
capacitor =
maximum
VDDIO
external
40pF
from
USPI1
USPI4
25.5 + t
30.0+ t
AT32UC3L016/32/64
Min
SAMPLE
0
0
SAMPLE
(2)
(2)
Max
13.6
8.5
Units
ns
64