ATMEGA32U2-AU Atmel, ATMEGA32U2-AU Datasheet - Page 215

• Manufacturer Part Number: ATMEGA32U2-AU
• Description: IC MCU 8BIT 32KB FLASH 32TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32U2-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFP, 32-VQFP
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AVR MEGA
• No. Of I/o's: 22
• Eeprom Memory Size: 1KB
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

21.18.11 UECFG0X – USB Endpoint Configuration 0 Register
7799D–AVR–11/10
• Bit 4 – STALLRQC: STALL Request Clear Handshake Bit
Writing this bit to one disables the pending STALL handshake mechanism triggered by
STALLRQ bit. This bit can not be write to zero, it is cleared by hardware immediately after the
write to one operation.
See
• Bit 3 – RSTDT: Reset Data Toggle Bit
Writing this bit to one allows to reset the data toggle bit field for the selected endpoint. This bit
can not be write to zero, it is cleared by hardware immediately after the write to one operation.
• Bits 2:1 – Res: Reserved
These bits are reserved and will always read as zero.
• Bit 0 – EPEN: Endpoint Enable Bit
Writing this bit to one enables the selected endpoint. When the endpoint is enabled it can be
configured and used by the USB controller. Endpoint 0 shall always be enabled after a hardware
or USB reset and participate in the device configuration. Writing this bit to zero disables the cur-
rent endpoint.
See
• Bit 7:6 – EPTYPE[1:0]: Endpoint Type Bits
These bits configure the endpoint type for the selected endpoint as shown in
Table 21-2.
• Bits 5:1 – Res: Reserved
These bits are reserved and will always read as zero.
• Bit 0 – EPDIR: Endpoint Direction Bit
Writing this bit to one configures the selected endpoint in the IN direction. Writing this bit to zero
configure the endpoint in the OUT direction. This bit is relevant for bulk, interrupt or isochronous
endpoints. Using this bit with a control endpoint has no effect (control endpoints are
bidirectional).
Bit
(0xEC)
Read/Write
Initial Value
“STALL request” on page 201
“Endpoint activation” on page 198
EPTYPE1
0
0
1
1
R/W
7
0
EPTYPE1:0
EPTYPE[1:0] Bits Settings
R/W
6
0
R
5
0
-
EPTYPE0
for more details.
0
1
0
1
for more details.
R
4
0
-
Control Type
Isochronous Type
Bulk Type
Interrupt Type
Endpoint Type Configuration
ATmega8U2/16U2/32U2
R
3
0
-
R
2
0
-
R
1
0
-
Table
EPDIR
R/W
0
0
21-2.
UECFG0X
215