DSPIC30F2011-30I/ML Microchip Technology, DSPIC30F2011-30I/ML Datasheet - Page 2

• Manufacturer Part Number: DSPIC30F2011-30I/ML
• Description: IC DSPIC MCU/DSP 12K 28QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2011-30I/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 12
• Flash Memory Size: 12KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DAF30-4 - DEVICE ATP FOR ICE4000
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F201130IML

dsPIC30F2011/2012
TABLE 2:
DS80450D-page 2
Operations
Note 1:
Controller
Compare
Compare
Interrupt
Module
Output
Output
Sleep
Mode
Timer
I
CPU
CPU
CPU
ADC
PSV
2
PLL
PLL
I
I/O
—
C™
2
C
Only those issues indicated in the last column apply to the current silicon revision.
Lock Status bit
Modification
Sleep Mode
Sleep Mode
PWM Mode
Slave Mode
Instructions
Multiplexed
Addressing
MAC Class
Instruction
Instruction
SILICON ISSUE SUMMARY
Feature
Address
with IC1
Port Pin
with ±4
DAW.b
DISI
10-bit
—
—
—
—
—
—
Number
Item
10.
12.
13.
14.
15.
16.
11.
1.
2.
3.
4.
5.
6.
7.
8.
9.
This issue was removed in the “B” revision of this document
(DS80450B).
Sequential MAC instructions, which prefetch data from Y data
space using ±4 address modification, will cause an address
error trap.
The Decimal Adjust instruction, DAW.b, may improperly clear
the Carry bit, C (SR<0>).
The DISI instruction will not disable interrupts if a DISI
instruction is executed in the same instruction cycle that the
DISI counter decrements to zero.
An interrupt occurring immediately after modifying the CPU
IPL, interrupt IPL, interrupt enable or interrupt flag may cause
an address error trap.
The Output Compare module will produce a glitch on the
output when an I/O pin is initially set high and the module is
configured to drive the pin low at a specified time.
Output compare will produce a glitch when loading 0% duty
cycle in PWM mode. It will also miss the next compare after
the glitch.
ADC event triggers from the INT0 pin will not wake-up the
device from Sleep mode if the SMPI bits are non-zero.
If 4x or 8x PLL mode is used, the input frequency range is
5 MHz-10 MHz instead of 4 MHz-10 MHz.
Execution of the Sleep instruction (PWRSAV #0) may cause
incorrect program operation after the device wakes up from
Sleep. The current consumption during Sleep may also
increase beyond the specifications listed in the device data
sheet.
Clock switching prevents the device from waking up from
Sleep.
The PLL LOCK Status bit (OSCCON<5>) can occasionally
get cleared and generate an oscillator failure trap even when
the PLL is still locked and functioning correctly.
An address error trap occurs in certain addressing modes
when accessing the first four bytes of any Program Space
Visibility (PSV) page.
The Port I/O pin multiplexed with the Input Capture 1 (IC1)
function cannot be used as a digital input pin when the UART
auto-baud feature is enabled.
The 10-bit slave does not set the RBF flag or load the
I2CxRCV register on address match if the Least Significant
bits (LSbs) of the address are the same as the 7-bit reserved
addresses.
The I
an I
2
C slave.
2
C module loses incoming data bytes when operating as
Issue Summary
© 2010 Microchip Technology Inc.
Revisions
Affected
A1
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(1)