DSPIC30F2011-30I/ML Microchip Technology, DSPIC30F2011-30I/ML Datasheet
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DSPIC30F2011-30I/ML
Specifications of DSPIC30F2011-30I/ML
Related parts for DSPIC30F2011-30I/ML
DSPIC30F2011-30I/ML Summary of contents
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... Family Silicon Errata and Data Sheet Clarification The dsPIC30F2011/2012 family devices that you have received conform functionally to the current Device Data Sheet (DS70139F), except for the anomalies described in this document. The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1 ...
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... TABLE 2: SILICON ISSUE SUMMARY Item Module Feature Number — — 1. CPU MAC Class 2. Instructions with ±4 Address Modification CPU 3. DAW.b Instruction CPU 4. DISI Instruction Interrupt — 5. Controller Output — 6. Compare Output PWM Mode 7. Compare ADC Sleep Mode 8. PLL — 9. Sleep — ...
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... Consumption in Sleep Mode Note 1: Only those issues indicated in the last column apply to the current silicon revision. © 2010 Microchip Technology Inc. dsPIC30F2011/2012 Issue Summary 2 When the I C module is configured for 10-bit addressing using the same address bits (A10 and A9) as other I devices, the A10 and A9 bits may not work as expected ...
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... Silicon Errata Issues Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (A1). 1. Module: N/A This issue was removed in the “B” revision of this document (DS80450B) ...
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... There is one level of DISI, so this macro saves and restores the DISI state. For temporarily modifying and restoring the CPU IPL, the mac- ros RESTORE_CPU_IPL can be used, as shown in Example 4. These macros also make use of the SET_CPU_IPL macro. dsPIC30F2011/2012 USING DISI USING SET_CPU_IPL MACRO \ \ and ...
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... EXAMPLE 4: USING SET_AND_SAVE_CPU_IPL AND RESTORE_CPU_IPL MACROS // Note: Macros defined in device include files #define SET_AND_SAVE_CPU_IPL (save_to, ipl){ \ save_to = SRbits.IPL; \ SET_CPU_IPL (ipl); } (void) 0; #define RESTORE_CPU_IPL (saved_to) SET_CPU_IPL (saved_to) #include "p30fxxxx.h" int save_to; SET_AND_SAVE_CPU_IPL (save_to RESTORE_CPU_IPL (save_to) For modification of the Interrupt 1 setting, the INTERRUPT_PROTECT macro can be used ...
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... Affected Silicon Revisions A1 X © 2010 Microchip Technology Inc. dsPIC30F2011/2012 8. Module: ADC ADC event triggers from the INT0 pin will not wake-up the device from Sleep mode if the SMPI bits are non-zero. This means that if the ADC is configured to generate an interrupt after a certain ...
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... Module: Sleep Mode Execution of the Sleep instruction (PWRSAV #0) may cause incorrect program operation after the device wakes up from Sleep. The current consumption during Sleep may also increase beyond the specifications listed in the device data sheet. Work arounds To avoid this issue, implement any of the following three work arounds, depending on the application requirements ...
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... Note: The above work around is recommended for users for whom application hardware changes are not possible. © 2010 Microchip Technology Inc. dsPIC30F2011/2012 Work around 3: Instead of executing a PWRSAV #0 instruction to put the device into Sleep mode, perform a clock switch to the 32 kHz Low-Power (LP) Oscillator with a 64:1 postscaler mode ...
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... Module: Timer When the timer is being operated in Asynchronous mode using the secondary oscillator (32.768 kHz) and the device is put into Sleep mode, a clock switch to any other oscillator mode before putting the device to Sleep prevents the timer from waking the device from Sleep. ...
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... RBF and I2COV bits are already set due to data 2 transfers between other I C nodes. © 2010 Microchip Technology Inc. dsPIC30F2011/2012 2. Check the status of the D_A flag and the I2COV flag in the I2CSTAT register when 2 executing the I C slave service routine. ...
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... Module 10-bit Addressing mode, some address matches do not set the RBF flag or load the receive register I2CxRCV, if the lower address byte matches the reserved particular, these include all addresses with the form XX0000XXXX and XX1111XXXX, with the following exceptions: • ...
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... ADC module by setting the ADC Module Disable bit in the corresponding Peripheral Module (PMDx) register, prior to executing a PWRSAV #0 instruction. Affected Silicon Revisions A1 X © 2010 Microchip Technology Inc. specifications Disable dsPIC30F2011/2012 DS80450D-page 13 ...
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... Data Sheet Clarifications The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS70139F): Note: Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. 1. Module: DC Characteristics: I/O Pin Input ...
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... Mode), 11 (Timer), 12 (PLL), 13 (PSV 2 Operations), 14 (I/O) and 15-19 (I C). This document replaces the following errata document: • DS80273, “dsPIC30F2011/2012 Rev. A1 Silicon Errata” Rev B Document (8/2009) Removed silicon issue 1 (EMUC2 Pin). The numbering for existing issues does not change. ...
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... NOTES: DS80450D-page 16 © 2010 Microchip Technology Inc. ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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