PIC18F97J60T-I/PT Microchip Technology, PIC18F97J60T-I/PT Datasheet - Page 407

• Manufacturer Part Number: PIC18F97J60T-I/PT
• Description: IC PIC MCU FLASH 64KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60T-I/PT

• Core Size: 8-Bit
• Program Memory Size: 128KB (64K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Type: FLASH
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 70
• Ram Memory Size: 3808Byte
• Cpu Speed: 41.667MHz
• No. Of Timers: 5
• No. Of: RoHS Compliant
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2AC164323 - MODULE SKT FOR 100TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

CALLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description
Words:
Cycles:
Example:
© 2009 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
operation
Decode
No
PC
PCLATH =
PCLATU =
W
PC
TOS
PCLATH =
PCLATU =
W
Q1
=
=
=
=
=
operation
Subroutine Call using WREG
CALLW
None
(PC + 2) → TOS,
(W) → PCL,
(PCLATH) → PCH,
(PCLATU) → PCU
None
First, the return address (PC + 2) is
pushed onto the return stack. Next, the
contents of W are written to PCL; the
existing value is discarded. Then, the
contents of PCLATH and PCLATU are
latched into PCH and PCU,
respectively. The second cycle is
executed as a NOP instruction while the
new next instruction is fetched.
Unlike CALL, there is no option to
update W, STATUS or BSR.
1
2
HERE
WREG
Read
0000
No
Q2
address (HERE)
10h
00h
06h
001006h
address (HERE + 2)
10h
00h
06h
CALLW
0000
Push PC to
operation
stack
No
Q3
0001
operation
operation
No
No
Q4
0100
PIC18F97J60 FAMILY
MOVSF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
1st word (source)
2nd word (destin.)
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
Decode
FSR2
Contents
of 85h
REG2
FSR2
Contents
of 85h
REG2
Q1
source addr
No dummy
Determine
operation
Move Indexed to f
MOVSF [z
0 ≤ z
0 ≤ f
((FSR2) + z
None
The contents of the source register are
moved to destination register ‘f
actual address of the source register is
determined by adding the 7-bit literal
offset ‘z
of FSR2. The address of the destination
register is specified by the 12-bit literal
‘f
can be anywhere in the 4096-byte data
space (000h to FFFh).
The MOVSF instruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
If the resultant source address points to
an indirect addressing register, the
value returned will be 00h.
2
2
MOVSF
d
read
’ in the second word. Both addresses
1110
1111
No
Q2
=
=
=
=
=
=
d
s
≤ 4095
≤ 127
s
’, in the first word, to the value
80h
33h
11h
80h
33h
33h
[05h], REG2
s
s
source addr
1011
ffff
], f
) → f
Determine
operation
d
No
Q3
d
DS39762E-page 407
0zzz
ffff
source reg
register ‘f’
(dest)
Read
Write
d
Q4
zzzz
ffff
’. The
s
d