PIC18F97J60T-I/PT Microchip Technology, PIC18F97J60T-I/PT Datasheet - Page 106

• Manufacturer Part Number: PIC18F97J60T-I/PT
• Description: IC PIC MCU FLASH 64KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60T-I/PT

• Core Size: 8-Bit
• Program Memory Size: 128KB (64K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Type: FLASH
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 70
• Ram Memory Size: 3808Byte
• Cpu Speed: 41.667MHz
• No. Of Timers: 5
• No. Of: RoHS Compliant
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2AC164323 - MODULE SKT FOR 100TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F97J60 FAMILY
EXAMPLE 6-3:
DS39762E-page 106
ERASE_BLOCK
RESTART_BUFFER
FILL_BUFFER
WRITE_BUFFER
WRITE_BYTE_TO_HREGS
PROGRAM_MEMORY
Required
Sequence
WRITING TO FLASH PROGRAM MEMORY
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
...
MOVLW
MOVWF
MOVFF
MOVWF
TBLWT+*
DECFSZ
BRA
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
BCF
DECFSZ
BRA
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
EECON1, WREN
EECON1, FREE
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
INTCON, GIE
D'16'
WRITE_COUNTER
D'64'
COUNTER
BUFFER_ADDR_HIGH
FSR0H
BUFFER_ADDR_LOW
FSR0L
D’64
COUNTER
POSTINC0, WREG
TABLAT
COUNTER
WRITE_BYTE_TO_HREGS
EECON1, WREN
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
INTCON, GIE
EECON1, WREN
WRITE_COUNTER
RESTART_BUFFER
; Load TBLPTR with the base
; address of the memory block
; enable write to memory
; enable Row Erase operation
; disable interrupts
; write 55h
; write 0AAh
; start erase (CPU stall)
; re-enable interrupts
; Need to write 16 blocks of 64 to write
; one erase block of 1024
; point to buffer
; read the new data from I2C, SPI,
; PSP, USART, etc.
; number of bytes in holding register
; get low byte of buffer data
; present data to table latch
; write data, perform a short write
; to internal TBLWT holding register.
; loop until buffers are full
; enable write to memory
; disable interrupts
; write 55h
; write 0AAh
; start program (CPU stall)
; re-enable interrupts
; disable write to memory
; done with one write cycle
; if not done replacing the erase block
© 2009 Microchip Technology Inc.