PIC24HJ16GP304-I/PT Microchip Technology, PIC24HJ16GP304-I/PT Datasheet - Page 19

• Manufacturer Part Number: PIC24HJ16GP304-I/PT
• Description: IC PIC MCU FLASH 16K 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ16GP304-I/PT

• Core Size: 16-Bit
• Program Memory Size: 16KB (5.5K x 24)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Number Of I /o: 35
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 13x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC24
• No. Of I/o's: 35
• Ram Memory Size: 2KB
• Cpu Speed: 40MIPS
• No. Of Timers: 4
• Processor Series: PIC24HJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 13 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.0
The PIC24HJ32GP202/204 and PIC24HJ16GP304
CPU modules have a 16-bit (data) modified Harvard
architecture with an enhanced instruction set and
addressing modes. The CPU has a 24-bit instruction
word with a variable length opcode field. The Program
Counter (PC) is 23 bits wide and addresses up to
4M x 24 bits of user program memory space. The
actual amount of program memory implemented varies
by
mechanism is used to help maintain throughput and
provides predictable execution. All instructions execute
in a single cycle, with the exception of instructions that
change the program flow, the double word move
(MOV.D)
Overhead-free, single-cycle program loop constructs
are supported using the REPEAT instruction, which is
interruptible at any point.
The PIC24HJ32GP202/204 and PIC24HJ16GP304
devices have sixteen, 16-bit working registers in the
programmer’s model. Each of the working registers can
serve as a data, address or address offset register. The
16th working register (W15) operates as a software
Stack Pointer (SP) for interrupts and calls.
The PIC24HJ32GP202/204 and PIC24HJ16GP304
instruction set includes many addressing modes and is
designed for optimum C compiler efficiency. For most
instructions,
PIC24HJ16GP304 is capable of executing a data (or
program data) memory read, a working register (data)
read, a data memory write and a program (instruction)
memory read per instruction cycle. As a result, three
parameter instructions can be supported, allowing
A + B = C operations to be executed in a single cycle.
A block diagram of the CPU is shown in Figure 3-1. The
programmer’s model for the PIC24HJ32GP202/204
and PIC24HJ16GP304 is shown in Figure 3-2.
 2009 Microchip Technology Inc.
Note 1: This data sheet summarizes the features
device.
2: Some registers and associated bits
CPU
instruction and the table instructions.
of
PIC24HJ16GP304 family of devices.
However, it is not intended to be a com-
prehensive reference source. To comple-
ment the information in this data sheet,
refer to “Section 2. CPU” (DS70204) of
the ”dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Microchip website (www.microchip.com).
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
PIC24HJ32GP202/204 and PIC24HJ16GP304
A
the
the
single-cycle
PIC24HJ32GP202/204
PIC24HJ32GP202/204
instruction
prefetch
and
and
Preliminary
3.1
The data space can be linearly addressed as 32K words
or 64 Kbytes using an Address Generation Unit (AGU).
The upper 32 Kbytes of the data space memory map can
optionally be mapped into program space at any 16K
program word boundary defined by the 8-bit Program
Space Visibility Page register (PSVPAG). The program to
data space mapping feature lets any instruction access
program space as if it were data space.
The data space also includes 2 Kbytes of DMA RAM,
which is primarily used for DMA data transfers, but this
may be used as general purpose RAM.
3.2
The PIC24HJ32GP202/204 and PIC24HJ16GP304
feature a 17-bit by 17-bit, single-cycle multiplier. The
multiplier
mixed-sign multiplication. Using a 17-bit by 17-bit
multiplier for 16-bit by 16-bit multiplication makes
mixed-sign multiplication possible.
The PIC24HJ32GP202/204 and PIC24HJ16GP304
supports 16/16 and 32/16 integer divide operations. All
divide instructions are iterative operations. They must
be executed within a REPEAT loop, resulting in a total
execution time of 19 instruction cycles. The divide
operation can be interrupted during any of those
19 cycles without loss of data.
A multi-bit data shifter is used to perform up to a 16-bit,
left or right shift in a single cycle.
Data Addressing Overview
Special MCU Features
can
perform
signed,
DS70289F-page 19
unsigned
and