PIC24HJ16GP304-I/PT Microchip Technology, PIC24HJ16GP304-I/PT Datasheet - Page 145

IC PIC MCU FLASH 16K 44TQFP

PIC24HJ16GP304-I/PT

Manufacturer Part Number
PIC24HJ16GP304-I/PT
Description
IC PIC MCU FLASH 16K 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 24Hr

Specifications of PIC24HJ16GP304-I/PT

Core Size
16-Bit
Program Memory Size
16KB (5.5K x 24)
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Core Processor
PIC
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Number Of I /o
35
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 13x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Controller Family/series
PIC24
No. Of I/o's
35
Ram Memory Size
2KB
Cpu Speed
40MIPS
No. Of Timers
4
Processor Series
PIC24HJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
2 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
35
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 13 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1004 - PIC24 BREAKOUT BOARDDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC24HJ16GP304-I/PT
Manufacturer:
MICROCHIP
Quantity:
367
Part Number:
PIC24HJ16GP304-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
16.0
The Inter-Integrated Circuit (I
complete hardware support for both Slave and
Multi-Master modes of the I
standard, with a 16-bit interface.
The I
• The SCLx pin is clock
• The SDAx pin is data.
The I
• I
• I
• I
• I
• Serial clock synchronization for I
• I
 2009 Microchip Technology Inc.
modes of operation.
master and slaves.
used as a handshake mechanism to suspend and
resume serial transfer (SCLREL control).
collision and arbitrates accordingly.
2
2
2
2
2
Note 1: This data sheet summarizes the features
C interface supporting both Master and Slave
C Slave mode supports 7-bit and 10-bit address
C Master mode supports 7-bit and 10-bit address
C port allows bidirectional transfers between
C supports multi-master operation, detects bus
2
2
C module has a 2-pin interface:
C module offers the following key features:
2: Some registers and associated bits
INTER-INTEGRATED
CIRCUIT™ (I
of
PIC24HJ16GP304 family of devices.
However, it is not intended to be a com-
prehensive reference source. To comple-
ment the information in this data sheet,
refer to “Section 19. Inter-Integrated
Circuit™ (I
”dsPIC33Fj/PIC24H Family Reference
Manual”, which is available from the
Microchip website (www.microchip.com).
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
PIC24HJ32GP202/204 and PIC24HJ16GP304
the
PIC24HJ32GP202/204
2
C™)” (DS70195) of the
2
C™)
2
C serial communication
2
C) module provides
2
C port can be
and
Preliminary
16.1
The hardware fully implements all the master and slave
functions of the I
specifications, as well as 7 and 10-bit addressing.
The I
master on an I
The following types of I
• I
• I
• I
For details about the communication sequence in each
of these modes, refer to the “PIC24H Family Reference
Manual”.
16.2
I2CxCON and I2CxSTAT are control and status
registers, respectively. The I2CxCON register is
readable and writable. The lower six bits of I2CxSTAT
are read-only. The remaining bits of the I2CSTAT are
read/write.
• I2CxRSR is the shift register used for shifting
• I2CxRCV is the receive buffer and the register to
• I2CxTRN is the transmit register to which bytes
• The I2CxADD register holds the slave address.
• A status bit, ADD10, indicates 10-bit Address
• I2CxBRG acts as the Baud Rate Generator
In receive operations, I2CxRSR and I2CxRCV together
form a double-buffered receiver. When I2CxRSR
receives a complete byte, it is transferred to I2CxRCV,
and an interrupt pulse is generated.
data.
which data bytes are written, or from which data
bytes are read.
are written during a transmit operation.
mode.
(BRG) reload value.
2
2
2
C slave operation with 7-bit address
C slave operation with 10-bit address
C master operation with 7-bit or 10-bit address
2
C module can operate either as a slave or a
Operating Modes
I
2
C Registers
2
C bus.
2
C Standard and Fast mode
2
C operation are supported:
DS70289F-page 145

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