ATMEGA3250-16AUR Atmel, ATMEGA3250-16AUR Datasheet - Page 14
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ATMEGA3250-16AUR
Manufacturer Part Number
ATMEGA3250-16AUR
Description
MCU AVR 32K FLASH 16MHZ 100TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA325-16AUR.pdf
(362 pages)
Specifications of ATMEGA3250-16AUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Part Number
Manufacturer
Quantity
Price
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6.6
6.7
2570M–AVR–04/11
Stack Pointer
Instruction Execution Timing
Figure 6-3.
In the different addressing modes these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the instruction set reference for details).
The Stack is mainly used for storing temporary data, for storing local variables and for storing
return addresses after interrupts and subroutine calls. The Stack Pointer Register always points
to the top of the Stack. Note that the Stack is implemented as growing from higher memory loca-
tions to lower memory locations. This implies that a Stack PUSH command decreases the Stack
Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt
Stacks are located. This Stack space in the data SRAM must be defined by the program before
any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to
point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack
with the PUSH instruction, and it is decremented by two when the return address is pushed onto
the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is
popped from the Stack with the POP instruction, and it is incremented by two when data is
popped from the Stack with return from subroutine RET or return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of
bits actually used is implementation dependent. Note that the data space in some implementa-
tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register
will not be present.
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
chip. No internal clock division is used.
Figure 6-4 on page 15
by the Harvard architecture and the fast-access Register File concept. This is the basic pipelin-
X-register
Y-register
Z-register
Bit
0x3E (0x5E)
0x3D (0x5D)
Read/Write
Initial Value
The X-, Y-, and Z-registers
SP15
R/W
SP7
R/W
15
7
0
0
15
7
R27 (0x1B)
15
7
R29 (0x1D)
15
7
R31 (0x1F)
SP14
shows the parallel instruction fetches and instruction executions enabled
SP6
R/W
R/W
14
6
0
0
SP13
SP5
R/W
R/W
13
5
0
0
XH
YH
ZH
0
CPU
, directly generated from the selected clock source for the
SP12
R/W
R/W
SP4
12
4
0
0
ATmega325/3250/645/6450
SP11
R/W
R/W
SP3
11
3
0
0
0
0
7
R26 (0x1A)
7
R28 (0x1C)
7
R30 (0x1E)
SP10
R/W
SP2
R/W
10
2
0
0
SP9
SP1
R/W
R/W
9
1
0
0
XL
YL
ZL
0
SP8
SP0
R/W
R/W
8
0
0
0
SPH
SPL
0
0
0
0
0
14
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