PIC18F46J11-I/PT Microchip Technology, PIC18F46J11-I/PT Datasheet

IC PIC MCU FLASH 64KB 44-TQFP

PIC18F46J11-I/PT

Manufacturer Part Number
PIC18F46J11-I/PT
Description
IC PIC MCU FLASH 64KB 44-TQFP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets

Specifications of PIC18F46J11-I/PT

Program Memory Type
FLASH
Program Memory Size
64KB (32K x 16)
Package / Case
44-TQFP, 44-VQFP
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
34
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
48 MHz
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164136, DM183022
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
Package
44TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
48 MHz
Operating Supply Voltage
2.5|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F46J11-I/PT
Manufacturer:
MICROCHIP
Quantity:
3 000
Part Number:
PIC18F46J11-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F46J11-I/PT
0
PIC18F46J11 Family
Data Sheet
28/44-Pin, Low-Power,
High-Performance Microcontrollers
with nanoWatt XLP Technology
© 2009 Microchip Technology Inc.
DS39932C

Related parts for PIC18F46J11-I/PT

PIC18F46J11-I/PT Summary of contents

Page 1

... High-Performance Microcontrollers © 2009 Microchip Technology Inc. PIC18F46J11 Family 28/44-Pin, Low-Power, with nanoWatt XLP Technology Data Sheet DS39932C ...

Page 2

... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

Page 3

... PIC18F46J11 FAMILY 28/44-Pin, Low-Power, High-Performance Microcontrollers Power Management Features with nanoWatt XLP™ for Extreme Low Power: • Deep Sleep mode: CPU off, Peripherals off, Currents Down and 850 nA with RTCC - Able to wake-up on external triggers, programmable WDT or RTCC alarm - Ultra Low-Power Wake-up (ULPWU) • ...

Page 4

... PIC18F46J11 FAMILY (1) PIC18F/LF Device PIC18F24J11 28 16K 3776 16 PIC18F25J11 28 32K 3776 16 PIC18F26J11 28 64K 3776 16 PIC18F44J11 44 16K 3776 22 PIC18F45J11 44 32K 3776 22 PIC18F46J11 44 64K 3776 22 PIC18LF24J11 28 16K 3776 16 PIC18LF25J11 28 32K 3776 16 PIC18LF26J11 28 64K 3776 16 PIC18LF44J11 44 16K 3776 22 PIC18LF45J11 44 32K 3776 22 PIC18LF46J11 44 64K 3776 22 Note 1: See Section 1.3 “ ...

Page 5

... Table 9-14, respectively. For details on configuring the PPS module, see Section 9.7 “Peripheral Pin Select (PPS)”. 2: See Section 25.3 “On-Chip Voltage Regulator” for details on how to connect the V 3: For the QFN package recommended that the bottom pad be connected to V © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY ...

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... PIC18F46J11 FAMILY Pin Diagrams (Continued) (1,3) 44-Pin QFN RC7/PMA4/RX1/DT1/RP18 RD4/PMD4/RP21 RD5/PMD5/RP22 RD6/PMD6/RP23 RD7/PMD7/RP24 RB0/AN12/INT0/RP3 RB1/AN10/PMBE/RTCC/RP4 RB2/AN8/CTEDG1/PMA3/REFO/RP5 Legend: RPn represents remappable pins. Note 1: Some input and output functions are routed through the Peripheral Pin Select (PPS) module and can be dynamically assigned to any of the RPn pins. For a list of the input and output functions, see Table 9-13 and Table 9-14, respectively. For details on configuring the PPS module, see Section 9.7 “ ...

Page 7

... RPn pins. For a list of the input and output functions, see Table 9-13 and Table 9-14, respectively. For details on configuring the PPS module, see Section 9.7 “Peripheral Pin Select (PPS)”. 2: See Section 25.3 “On-Chip Voltage Regulator” for details on how to connect the V © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY ...

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... PIC18F46J11 FAMILY Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 11 2.0 Oscillator Configurations ............................................................................................................................................................ 31 3.0 Low-Power Modes...................................................................................................................................................................... 41 4.0 Reset .......................................................................................................................................................................................... 57 5.0 Memory Organization ................................................................................................................................................................. 71 6.0 Flash Program Memory .............................................................................................................................................................. 97 7 Hardware Multiplier.......................................................................................................................................................... 107 8.0 Interrupts .................................................................................................................................................................................. 109 9.0 I/O Ports ................................................................................................................................................................................... 125 10.0 Parallel Master Port (PMP)....................................................................................................................................................... 165 11.0 Timer0 Module ......................................................................................................................................................................... 191 12 ...

Page 9

... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY DS39932C-page 9 ...

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... PIC18F46J11 FAMILY NOTES: DS39932C-page 10 © 2009 Microchip Technology Inc. ...

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... Microchip Technology Inc. PIC18F46J11 FAMILY 1.1.2 OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18F46J11 family offer five different oscillator options, allowing users a range of choices in developing application hardware. These include: • Two Crystal modes using crystals or ceramic resonators. ...

Page 12

... Section 28.0 “Electrical Characteristics” for time-out periods. 1.3 Details on Individual Family Devices Devices in the PIC18F46J11 family are available in 28-pin and 44-pin packages. Block diagrams for the two groups are shown in Figure 1-1 and Figure 1-2. The devices are differentiated from each other in two ways: • ...

Page 13

... Interrupt Sources I/O Ports Timers Enhanced Capture/Compare/PWM Modules Serial Communications Parallel Communications (PMP/PSP) 10-Bit Analog-to-Digital Module Resets (and Delays) Instruction Set Packages © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY PIC18F24J11 PIC18F25J11 DC – 48 MHz DC – 48 MHz 16K 32K 8,192 16,384 3.8K 3.8K ...

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... PIC18F46J11 FAMILY FIGURE 1-1: PIC18F2XJ11 (28-PIN) BLOCK DIAGRAM Table Pointer<21> inc/dec logic 21 20 Address Latch Program Memory (16 Kbytes-64 Kbytes) Data Latch 8 Instruction Bus <16> Timing Generation OSC2/CLKO OSC1/CLKI 8 MHz INTOSC INTRC Oscillator Precision Band Gap Reference Voltage Regulator V /V DDCORE CAP ...

Page 15

... LVD 10-Bit PMP CTMU ECCP1 Note 1: See Table 1-4 for I/O port pin descriptions. 2: BOR functionality is provided when the on-chip voltage regulator is enabled. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Data Latch 8 8 Data Memory (3.8 Kbytes) PCLATU PCLATH Address Latch ...

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... PIC18F46J11 FAMILY TABLE 1-3: PIC18F2XJ11 PINOUT I/O DESCRIPTIONS Pin Number 28-SPDIP/ Pin Name SSOP/ SOIC MCLR 1 OSC1/CLKI/RA7 9 OSC1 CLKI (1) RA7 OSC2/CLKO/RA6 10 OSC2 CLKO (1) RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function ...

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... ST = Schmitt Trigger input with CMOS levels I = Input P = Power DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Pin Buffer Type Type 28-QFN PORTA is a bidirectional I/O port. 27 I/O DIG Digital I/O ...

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... PIC18F46J11 FAMILY TABLE 1-3: PIC18F2XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number 28-SPDIP/ Pin Name SSOP/ SOIC RB0/AN12/INT0/RP3 21 RB0 AN12 INT0 RP3 RB1/AN10/RTCC/RP4 22 RB1 AN10 RTCC RP4 RB2/AN8/CTEDG1/ 23 REFO/RP5 RB2 AN8 CTEDG1 REFO RP5 RB3/AN9/CTEDG2/RP6 24 RB3 AN9 CTEDG2 RP6 RB4/KBI0/RP7 25 RB4 KBI0 ...

Page 19

... ST = Schmitt Trigger input with CMOS levels I = Input P = Power DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Pin Buffer Type Type 28-QFN PORTB (continued) 24 I/O DIG Digital I/O ...

Page 20

... PIC18F46J11 FAMILY TABLE 1-3: PIC18F2XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number 28-SPDIP/ Pin Name SSOP/ SOIC RC0/T1OSO/T1CKI/RP11 11 RC0 T1OSO T1CKI RP11 RC1/T1OSI/RP12 12 RC1 T1OSI RP12 RC2/AN11/CTPLS/RP13 13 RC2 AN11 CTPLS RP13 RC3/SCK1/SCL1/RP14 14 RC3 SCK1 SCL1 RP14 RC4/SDI1/SDA1/RP15 15 RC4 SDI1 SDA1 RP15 RC5/SDO1/RP16 ...

Page 21

... ST = Schmitt Trigger input with CMOS levels I = Input P = Power DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Pin Buffer Type Type 28-QFN 5 P — Ground reference for logic and I/O pins. ...

Page 22

... PIC18F46J11 FAMILY TABLE 1-4: PIC18F4XJ11 PINOUT I/O DESCRIPTIONS Pin Number Pin Name QFN MCLR OSC1/CLKI/RA7 OSC1 CLKI (1) RA7 OSC2/CLKO/RA6 OSC2 CLKO (1) RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. ...

Page 23

... ST = Schmitt Trigger input with CMOS levels I = Input P = Power DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Pin Buffer 44- 44- Type Type TQFP PORTA is a bidirectional I/O port. ...

Page 24

... PIC18F46J11 FAMILY TABLE 1-4: PIC18F4XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name QFN RB0/AN12/INT0/RP3 RB0 AN12 INT0 RP3 RB1/AN10/PMBE/RTCC/RP4 RB1 AN10 PMBE RTCC RP4 RB2/AN8/CTEDG1/PMA3/REFO/ RP5 RB2 AN8 CTEDG1 PMA3 REFO RP5 RB3/AN9/CTEDG2/PMA2/RP6 RB3 AN9 CTEDG2 PMA2 RP6 Legend: TTL = TTL compatible input ...

Page 25

... ST = Schmitt Trigger input with CMOS levels I = Input P = Power DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Pin Buffer 44- 44- Type Type TQFP PORTB (continued) ...

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... PIC18F46J11 FAMILY TABLE 1-4: PIC18F4XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name QFN RC0/T1OSO/T1CKI/RP11 RC0 T1OSO T1CKI RP11 RC1/T1OSI/RP12 RC1 T1OSI RP12 RC2/AN11/CTPLS/RP13 RC2 AN11 CTPLS RP13 RC3/SCK1/SCL1/RP14 RC3 SCK1 SCL1 RP14 RC4/SDI1/SDA1/RP15 RC4 SDI1 SDA1 RP15 RC5/SDO1/RP16 RC5 SDO1 ...

Page 27

... ST = Schmitt Trigger input with CMOS levels I = Input P = Power DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Pin Buffer 44- 44- Type Type TQFP PORTC (continued) ...

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... PIC18F46J11 FAMILY TABLE 1-4: PIC18F4XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name QFN RD0/PMD0/SCL2 RD0 PMD0 SCL2 RD1/PMD1/SDA2 RD1 PMD1 SDA2 RD2/PMD2/RP19 RD2 PMD2 RP19 RD3/PMD3/RP20 RD3 PMD3 RP20 RD4/PMD4/RP21 RD4 PMD4 RP21 RD5/PMD5/RP22 RD5 PMD5 RP22 RD6/PMD6/RP23 RD6 PMD6 ...

Page 29

... ST = Schmitt Trigger input with CMOS levels I = Input P = Power DIG = Digital output Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Pin Buffer 44- 44- Type Type TQFP PORTE is a bidirectional I/O port. ...

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... PIC18F46J11 FAMILY NOTES: DS39932C-page 30 © 2009 Microchip Technology Inc. ...

Page 31

... Phase Locked Loop (PLL). Its use is described in Section 2.2.5.1 “OSCTUNE Register”. 2.2 Oscillator Types PIC18F46J11 family devices can be operated in eight distinct oscillator modes. Users can program the FOSC<2:0> Configuration bits to select one of the modes listed in Table 2-1. For oscillator modes which ...

Page 32

... PIC18F46J11 FAMILY 2.2.1 OSCILLATOR MODES Figure 2-1 helps in understanding the oscillator structure of the PIC18F46J11 family of devices. FIGURE 2-1: PIC18F46J11 FAMILY CLOCK DIAGRAM Primary Oscillator OSC2 OSCTUNE<7> Sleep OSC1 Secondary Oscillator T1OSO T1OSCEN Enable Oscillator T1OSI OSCCON<6:4> Internal Oscillator Block 8 MHz Source ...

Page 33

... Resonators Used: 4.0 MHz 8.0 MHz 16.0 MHz © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY TABLE 2-3: Osc Type HS Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation. These values are not optimized ...

Page 34

... DS39932C-page 34 2.2.5 INTERNAL OSCILLATOR BLOCK The PIC18F46J11 family devices include an internal oscillator block which generates two different clock signals; either can be used as the microcontroller’s clock source. The internal oscillator may eliminate the need for external oscillator circuits on the OSC1 and/or OSC2 pins ...

Page 35

... INTOSC source. Any changes in INTOSC across voltage and temperature are not necessarily reflected by changes in INTRC and vice versa. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 2.2.5.3 Compensating for INTOSC Drift It is possible to adjust the INTOSC frequency by modifying the value in the OSCTUNE register. This has no effect on the INTRC clock source frequency ...

Page 36

... Switching Like previous PIC18 enhanced PIC18F46J11 family includes a feature that allows the device clock source to be switched from the main oscillator to an alternate, low-frequency clock source. PIC18F46J11 family devices offer two alternate clock sources. When an alternate clock source is enabled, the various power-managed operating modes are available ...

Page 37

... Timer1 oscillator starts. 2.3.2 OSCILLATOR TRANSITIONS PIC18F46J11 family devices contain circuitry to prevent clock “glitches” when switching between clock sources. A short pause in the device clock occurs dur- ing the clock switch. The length of this pause is the sum ...

Page 38

... PIC18F46J11 FAMILY REGISTER 2-2: OSCCON: OSCILLATOR CONTROL REGISTER (ACCESS FD3h) R/W-0 R/W-1 R/W-1 IDLEN IRCF2 IRCF1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 IDLEN: Idle Enable bit 1 = Device enters Idle mode on SLEEP instruction 0 = Device enters Sleep mode on SLEEP instruction bit 6-4 IRCF< ...

Page 39

... Reference Clock Output In addition to the peripheral clock/4 output in certain oscillator modes, the device clock in the PIC18F46J11 family can also be configured to provide a reference clock output signal to a port pin. This feature is avail- able in all oscillator configurations and allows the user to select a greater range of clock submultiples to drive external devices in the application ...

Page 40

... PIC18F46J11 FAMILY 2.5 Effects of Power-Managed Modes on Various Clock Sources When the PRI_IDLE mode is selected, the designated primary oscillator continues to interruption. In secondary clock modes (SEC_RUN and SEC_IDLE), the Timer1 oscillator is operating and providing the device clock. The Timer1 oscillator may also run in all power-managed modes if required to clock Timer1 or Timer3 ...

Page 41

... The power-managed modes include power-saving features offered on previous PIC devices, such as clock switching, ULPWU and Sleep mode. In addition, the PIC18F46J11 family devices add a new power-managed Deep Sleep mode. 3.1 Selecting Power-Managed Modes Selecting a power-managed mode requires these decisions: • Will the CPU be clocked? • ...

Page 42

... PIC18F46J11 FAMILY TABLE 3-1: LOW-POWER MODES DSCONH<7> OSCCON<7,1:0> Mode (1) (1) DSEN IDLEN SCS<1:0> Sleep 0 0 Deep 1 0 (2) Sleep PRI_RUN N/A 0 SEC_RUN N/A 0 RC_RUN N/A 0 PRI_IDLE 0 1 SEC_IDLE 0 1 RC_IDLE 0 1 Note 1: IDLEN and DSEN reflect their values when the SLEEP instruction is executed. ...

Page 43

... T OST OSC © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Figure 3-2). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock would be providing the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run ...

Page 44

... PIC18F46J11 FAMILY 3.2.3 RC_RUN MODE In RC_RUN mode, the CPU and peripherals are clocked from the internal oscillator; the primary clock is shut down. This mode provides the best power conser- vation of all the Run modes while still executing code. It works well for user applications, which are not highly timing-sensitive or do not require high-speed clocks at all times ...

Page 45

... T OST OSC PLL © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY When a wake event occurs in Sleep mode (by interrupt, Reset or WDT time-out), the device will not be clocked until the clock source selected by the SCS<1:0> bits becomes ready (see Figure 3-6 will be clocked from the internal oscillator if either the Two-Speed Start-up or the FSCM is enabled (see Section 25 ...

Page 46

... PIC18F46J11 FAMILY 3.4 Idle Modes The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to ‘1’ when a SLEEP instruction is executed, the peripherals will be clocked from the clock source selected using the SCS< ...

Page 47

... TRANSITION TIMING FOR ENTRY TO IDLE MODE OSC1 CPU Clock Peripheral Clock Program PC Counter FIGURE 3-8: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE Q1 OSC1 CPU Clock Peripheral Clock Program Counter Wake Event © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY CSD DS39932C-page 47 ...

Page 48

... PIC18F46J11 FAMILY 3.4.3 RC_IDLE MODE In RC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the internal oscillator block. This mode allows for controllable power conservation during Idle periods. From RC_RUN, this mode is entered by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, first set IDLEN, then clear the SCS bits and execute SLEEP ...

Page 49

... Deep Sleep, and will remain valid throughout an entire Deep Sleep entry and wake-up sequence. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 3.6.2 I/O PINS DURING DEEP SLEEP During Deep Sleep, the general purpose I/O pins will retain their previous states ...

Page 50

... PIC18F46J11 FAMILY 3.6.3 DEEP SLEEP WAKE-UP SOURCES While in Deep Sleep mode, the device can be awakened by a MCLR, POR, RTCC, INT0 I/O pin interrupt, DSWDT or ULPWU event. After waking, the device per- forms a POR. When the device is released from Reset, code execution will begin at the device’s Reset vector. ...

Page 51

... For more information on configuring this peripheral, see Section 3.7 Low-Power Wake-up”. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 3.6.8 DEEP SLEEP FAULT DETECTION If during Deep Sleep the device is subjected to unusual operating conditions, such as an Electrostatic Dis- charge (ESD) event possible that the internal circuit states used by the Deep Sleep module could become corrupted ...

Page 52

... PIC18F46J11 FAMILY 3.6.9 DEEP SLEEP MODE REGISTERS Deep Sleep mode registers are Register 3-1 through Register 3-6. REGISTER 3-1: DSCONH: DEEP SLEEP CONTROL HIGH BYTE REGISTER (BANKED F4Dh) R/W-0 U-0 U-0 (1) DSEN — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘ ...

Page 53

... All register bits are maintained unless: V Sleep, or, the device is in Deep Sleep and the dedicated DSBOR is enabled and V DSBOR threshold, or DSBOR is enabled or disabled, but V © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY (1) R/W-xxxx U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...

Page 54

... PIC18F46J11 FAMILY REGISTER 3-5: DSWAKEH: DEEP SLEEP WAKE HIGH BYTE REGISTER (BANKED F4Bh) U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-1 Unimplemented: Read as ‘0’ bit 0 DSINT0: Interrupt-on-Change bit ...

Page 55

... Also in Sleep mode, only the remappable output func- tion, ULPWU, will output this bit value to an RPn pin for externally detecting wake-up events. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY See Example 3-1 for initializing the ULPWU module. Note: For module-related bit definitions, see the WDTCON “ ...

Page 56

... PIC18F46J11 FAMILY EXAMPLE 3-1: ULTRA LOW-POWER WAKE-UP INITIALIZATION //********************************************************************************* //Configure a remappable output pin with interrupt capability //for ULPWU function (RP21 => RD4/INT1 in this example) //********************************************************************************* RPOR21 = 13;// ULPWU function mapped to RP21/RD4 RPINR1 = 21;// INT1 mapped to RP21 (RD4) //*************************** //Charge the capacitor on RA0 //*************************** TRISAbits.TRISA0 = 0; PORTAbits.RA0 = 1; for < 10000; i++) Nop(); ...

Page 57

... RESET The PIC18F46J11 family of devices differentiates among various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during power-managed modes d) Watchdog Timer (WDT) Reset execution) e) Configuration Mismatch (CM) f) Brown-out Reset (BOR) g) RESET Instruction h) Stack Full Reset i) Stack Underflow Reset ...

Page 58

... PIC18F46J11 FAMILY REGISTER 4-1: RCON: RESET CONTROL REGISTER (ACCESS FD0h) R/W-0 U-0 R/W-1 IPEN — CM bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 Unimplemented: Read as ‘ ...

Page 59

... Reset values and the contents of the DSGPR0 and DSGPR1 holding registers will be lost. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Additionally, if any I/O pins had been configured as out- puts during Deep Sleep, these pins will be tri-stated and the device will no longer be held in Deep Sleep. ...

Page 60

... Electrostatic always enabled. The main function is to ensure that the device voltage is stable before code is executed. The Power-up Timer (PWRT) of the PIC18F46J11 family devices is a 5-bit counter which uses the INTRC source as the clock input. This yields an approximate time interval μ ms. While the PWRT is counting, the device is held in Reset ...

Page 61

... TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET FIGURE 4-5: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY T PWRT T PWRT , V RISE > 3. PWRT ): CASE 1 DD ...

Page 62

... PIC18F46J11 FAMILY 4.7 Reset State of Registers Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation ...

Page 63

... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. 5: Not implemented for PIC18F2XJ11 devices. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset, RESET Instruction ...

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... PIC18F46J11 FAMILY TABLE 4-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices POSTINC2 PIC18F2XJ11 PIC18F4XJ11 POSTDEC2 PIC18F2XJ11 PIC18F4XJ11 PREINC2 PIC18F2XJ11 PIC18F4XJ11 PLUSW2 PIC18F2XJ11 PIC18F4XJ11 FSR2H PIC18F2XJ11 PIC18F4XJ11 FSR2L PIC18F2XJ11 PIC18F4XJ11 STATUS PIC18F2XJ11 PIC18F4XJ11 TMR0H PIC18F2XJ11 PIC18F4XJ11 TMR0L PIC18F2XJ11 PIC18F4XJ11 T0CON ...

Page 65

... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. 5: Not implemented for PIC18F2XJ11 devices. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset, RESET Instruction ...

Page 66

... PIC18F46J11 FAMILY TABLE 4-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices RCSTA2 PIC18F2XJ11 PIC18F4XJ11 OSCTUNE PIC18F2XJ11 PIC18F4XJ11 T1GCON PIC18F2XJ11 PIC18F4XJ11 RTCVALH PIC18F2XJ11 PIC18F4XJ11 RTCVALL PIC18F2XJ11 PIC18F4XJ11 T3GCON PIC18F2XJ11 PIC18F4XJ11 (5) TRISE PIC18F2XJ11 PIC18F4XJ11 (5) TRISD PIC18F2XJ11 PIC18F4XJ11 TRISC PIC18F2XJ11 PIC18F4XJ11 TRISB ...

Page 67

... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. 5: Not implemented for PIC18F2XJ11 devices. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset, RESET Instruction ...

Page 68

... PIC18F46J11 FAMILY TABLE 4-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices PMEH PIC18F2XJ11 PIC18F4XJ11 PMEL PIC18F2XJ11 PIC18F4XJ11 PMSTATH PIC18F2XJ11 PIC18F4XJ11 PMSTATL PIC18F2XJ11 PIC18F4XJ11 (5) CVRCON PIC18F2XJ11 PIC18F4XJ11 ANCON1 PIC18F2XJ11 PIC18F4XJ11 ANCON0 PIC18F2XJ11 PIC18F4XJ11 ODCON1 PIC18F2XJ11 PIC18F4XJ11 ODCON2 PIC18F2XJ11 PIC18F4XJ11 ODCON3 ...

Page 69

... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. 5: Not implemented for PIC18F2XJ11 devices. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset, RESET Instruction ...

Page 70

... PIC18F46J11 FAMILY NOTES: DS39932C-page 70 © 2009 Microchip Technology Inc. ...

Page 71

... Accessing a location between the upper boundary of the physically implemented memory and the 2-Mbyte address returns all ‘0’s (a NOP instruction). The PIC18F46J11 family offers a range of on-chip Flash program memory sizes, from 16 Kbytes (up to 8,192 single-word (32,768 single-word instructions). ...

Page 72

... CONFIG1 at the lowest address and ending with the upper byte of CONFIG4. Table 5-1 provides the actual addresses of the Flash Configuration Word for devices in the PIC18F46J11 family. Figure 5-2 displays their location in the memory map with other memory vectors. Additional details on the device Configuration Words are provided in Section 25.1 “ ...

Page 73

... TOSL 00h 1Ah 34h © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer (SP), STKPTR. The stack space is not part of either program or data space. The Stack Pointer is readable and writable, and the address on the top of the stack is readable and writable through the Top-of-Stack Special Function Registers (SFRs) ...

Page 74

... PIC18F46J11 FAMILY 5.1.4.2 Return Stack Pointer (STKPTR) The STKPTR register (Register 5-1) contains the Stack Pointer value, the STKFUL (Stack Full) and the STKUNF (Stack Underflow) status bits. The value of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the stack and decrements after values are popped off the stack ...

Page 75

... SUB1 • RETURN FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 5.1.6 LOOK-UP TABLES IN PROGRAM MEMORY There may be programming situations that require the creation of data structures or look-up tables in program memory. For PIC18 devices, look-up tables can be implemented in two ways: • ...

Page 76

... PIC18F46J11 FAMILY 5.2 PIC18 Instruction Cycle 5.2.1 CLOCKING SCHEME The microcontroller clock input, whether from an internal or external source, is internally divided by ‘4’ to generate four non-overlapping quadrature clocks (Q1, Q2, Q3 and Q4). Internally, the PC is incremented on every Q1; the instruction is fetched from the program memory and latched into the Instruction Register (IR) during Q4 ...

Page 77

... ADDWF © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY The CALL and GOTO instructions have the absolute program memory address embedded into the instruc- tion. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC< ...

Page 78

... The memory space is divided into as many as 16 banks that contain 256 bytes each. The PIC18F46J11 family implements all available banks and provides 3.8 Kbytes of data memory available to the user. Figure 5-6 provides the data memory organization for the devices ...

Page 79

... FIGURE 5-6: DATA MEMORY MAP FOR PIC18F46J11 FAMILY DEVICES BSR3:BSR0 00h = 0000 Bank 0 FFh 00h = 0001 Bank 1 FFh 00h = 0010 Bank 2 FFh 00h = 0011 Bank 3 FFh 00h = 0100 Bank 4 FFh 00h = 0101 Bank 5 FFh 00h = 0110 Bank 6 FFh 00h = 0111 Bank 7 ...

Page 80

... PIC18F46J11 FAMILY FIGURE 5-7: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) (1) BSR (2) Bank Select Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 2: The MOVFF instruction embeds the entire 12-bit address in the instruction. ...

Page 81

... PMADDRx is used in Master modes and PMDOUTx is used in Slave modes. 5: Reserved: Do not write to this location. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY ALU’s STATUS register is described later in this section. Registers related to the operation of the peripheral features are described in the chapter for that peripheral. ...

Page 82

... PIC18F46J11 FAMILY TABLE 5-3: NON-ACCESS BANK SPECIAL FUNCTION REGISTER MAP Address Name Address Name F5Fh PMCONH F3Fh RTCCFG F5Eh PMCONL F3Eh RTCCAL F5Dh PMMODEH F3Dh REFOCON F5Ch PMMODEL F3Ch PADCFG1 F5Bh PMDOUT2H F3Bh F5Ah PMDOUT2L F3Ah F59h PMDIN2H F39h F58h PMDIN2L ...

Page 83

... SFR address. The operating mode of the MSSP modules determines which register is being accessed. See Section 18.5.3.4 “7-Bit Address Masking Mode” for additional details. TABLE 5-4: REGISTER FILE SUMMARY (PIC18F46J11 FAMILY) File Name Bit 7 Bit 6 Bit 5 TOSU — ...

Page 84

... PIC18F46J11 FAMILY TABLE 5-4: REGISTER FILE SUMMARY (PIC18F46J11 FAMILY) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 FSR1H — — FSR1L Indirect Data Memory Address Pointer 1 Low Byte BSR — — INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) POSTINC2 Uses contents of FSR2 to address data memory – ...

Page 85

... TABLE 5-4: REGISTER FILE SUMMARY (PIC18F46J11 FAMILY) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 PSTR2CON CMPL1 CMPL0 ECCP2AS ECCP2ASE ECCP2AS2 ECCP2AS1 ECCP2AS0 ECCP2DEL P2RSEN P2DC6 P2DC5 CCPR2H Capture/Compare/PWM Register 2 High Byte CCPR2L Capture/Compare/PWM Register 2 Low Byte CCP2CON P2M1 P2M0 DC2B1 CTMUCONH CTMUEN — ...

Page 86

... PIC18F46J11 FAMILY TABLE 5-4: REGISTER FILE SUMMARY (PIC18F46J11 FAMILY) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 ALRMRPT ARPT7 ARPT6 ARPT5 ALRMVALH Alarm Value Register Window High Byte, Based on ALRMPTR<1:0> ALRMVALL Alarm Value Register Window Low Byte, Based on ALRMPTR<1:0> LATE — — LATD ...

Page 87

... TABLE 5-4: REGISTER FILE SUMMARY (PIC18F46J11 FAMILY) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 TXADDRH — — RXADDRL SPI DMA Receive Data Pointer Low Byte RXADDRH — — DMABCL SPI DMA Byte Count Low Byte DMABCH — — (5) PMCONH PMPEN — PSIDL ...

Page 88

... PIC18F46J11 FAMILY TABLE 5-4: REGISTER FILE SUMMARY (PIC18F46J11 FAMILY) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 RPINR12 — — RPINR8 — — RPINR7 — — RPINR6 — — RPINR4 — — RPINR3 — — RPINR2 — — RPINR1 — — (5) RPOR24 — ...

Page 89

... For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY register then reads back as ‘000u u1uu’ recom- mended, therefore, that only BCF, BSF, SWAPF, MOVFF ...

Page 90

... PIC18F46J11 FAMILY 5.4 Data Addressing Modes Note: The execution of some instructions in the core PIC18 instruction set is changed when the PIC18 extended instruction set is enabled. See Section 5.6 “Data Memory and the Extended Instruction Set” for more information. While the program memory can be addressed in only one way, through the PC, information in the data memory space can be addressed in several ways ...

Page 91

... FCCh will be added to that of the W register and stored back in FCCh. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY SFR space but are not physically implemented. Read- ing or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L ...

Page 92

... PIC18F46J11 FAMILY 5.4.3.2 FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these are “virtual” registers that cannot be indirectly read or written to. Accessing these registers actually accesses the associated FSR register pair, but also performs a specific action on its stored value ...

Page 93

... Address Pointer specified by FSR2. The offset and the contents of FSR2 are added to obtain the target address of the operation. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 5.6.2 INSTRUCTIONS AFFECTED BY INDEXED LITERAL OFFSET MODE Any of the core PIC18 instructions that can use Direct Addressing are potentially affected by the Indexed Literal Offset Addressing mode ...

Page 94

... PIC18F46J11 FAMILY FIGURE 5-9: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF (Opcode: 0010 01da ffff ffff) When and f ≥ 60h: The instruction executes in Direct Forced mode. ‘f’ is interpreted as a location in the Access RAM between 060h and FFFh ...

Page 95

... BSR. F60h FFFh © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Remapping of the Access Bank applies only to opera- tions using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue to use Direct Addressing as before. Any Indirect or ...

Page 96

... PIC18F46J11 FAMILY NOTES: DS39932C-page 96 © 2009 Microchip Technology Inc. ...

Page 97

... Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 6.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...

Page 98

... PIC18F46J11 FAMILY FIGURE 6-2: TABLE WRITE OPERATION (1) Table Pointer TBLPTRU TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of 64 holding registers, the address of which is determined by TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section 6.5 “Writing to Flash Program Memory”. ...

Page 99

... Initiates a program memory erase cycle or write cycle (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software Write cycle is complete bit 0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY R/W-0 R/W-x R/W-0 FREE WRERR WREN U = Unimplemented bit, read as ‘ ...

Page 100

... PIC18F46J11 FAMILY 6.2.2 TABLE LATCH REGISTER (TABLAT) The Table Latch (TABLAT 8-bit register mapped into the Special Function Register (SFR) space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 6.2.3 TABLE POINTER REGISTER ...

Page 101

... MOVF TABLAT, W MOVWF WORD_ODD © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...

Page 102

... PIC18F46J11 FAMILY 6.4 Erasing Flash Program Memory The minimum erase block is 512 words or 1024 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be bulk erased. Word erase in the Flash array is not supported. When initiating an erase sequence from the micro- controller itself, a block of 1024 bytes of program memory is erased ...

Page 103

... The on-chip timer controls the write time. The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device. Note 1: Unlike previous PIC the PIC18F46J11 family do not reset the holding registers after a write occurs. The holding registers must be cleared or overwritten sequence. ...

Page 104

... PIC18F46J11 FAMILY EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY MOVLW CODE_ADDR_UPPER MOVWF TBLPTRU MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL ERASE_BLOCK BSF EECON1, WREN BSF EECON1, FREE BCF INTCON, GIE MOVLW 55h MOVWF EECON2 MOVLW 0AAh MOVWF EECON2 BSF EECON1, WR BSF ...

Page 105

... FLASH PROGRAM MEMORY WRITE SEQUENCE (WORD PRORAMMING). The PIC18F46J11 family of devices has a feature that allows programming a single word (two bytes). This feature is enabled when the WPROG bit is set. If the memory location is already erased, the following sequence is required to enable this feature: 1 ...

Page 106

... PIC18F46J11 FAMILY 6.5.3 WRITE VERIFY Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. 6.5.4 UNEXPECTED TERMINATION OF ...

Page 107

... Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY EXAMPLE 7- UNSIGNED MULTIPLY ROUTINE MOVF ARG1 MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL EXAMPLE 7-2: ...

Page 108

... PIC18F46J11 FAMILY Example 7-3 provides the instruction sequence for unsigned multiplication. Equation 7-1 provides the algorithm that is used. The 32-bit result is stored in four registers (RES<3:0>). EQUATION 7- UNSIGNED MULTIPLICATION ALGORITHM RES3:RES0 = ARG1H:ARG1L · ARG2H:ARG2L 16 = (ARG1H · ARG2H · (ARG1H · ARG2L · 2 ...

Page 109

... INTERRUPTS Devices of the PIC18F46J11 family have multiple inter- rupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high-priority level or a low-priority level. The high-priority interrupt vector is at 0008h and the low-priority interrupt vector is at 0018h. High-priority interrupt events will interrupt any low-priority interrupts that may be in progress ...

Page 110

... PIC18F46J11 FAMILY FIGURE 8-1: PIC18F46J11 FAMILY INTERRUPT LOGIC PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:0> PIE2<7:0> IPR2<7:0> PIR3<7:0> PIE3<7:0> IPR3<7:0> High-Priority Interrupt Generation Low-Priority Interrupt Generation PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:0> PIE2<7:0> IPR2<7:0> PIR3<7:0> PIE3<7:0> IPR3<7:0> DS39932C-page 110 TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF ...

Page 111

... Note 1: A mismatch condition will continue to set this bit. Reading PORTB and waiting 1 T condition and allow the bit to be cleared. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit ...

Page 112

... PIC18F46J11 FAMILY REGISTER 8-2: INTCON2: INTERRUPT CONTROL REGISTER 2 (ACCESS FF1h) R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values ...

Page 113

... Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY R/W-0 R/W-0 R/W-0 ...

Page 114

... PIC18F46J11 FAMILY 8.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Request (Flag) registers (PIR1, PIR2, PIR3). REGISTER 8-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 (ACCESS F9Eh) ...

Page 115

... No TMR1/TMR3 register capture occurred Compare mode TMR1/TMR3 register compare match occurred (must be cleared in software TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY U-0 R/W-0 R/W-0 BCL1IF LVDIF — Unimplemented bit, read as ‘0’ ...

Page 116

... PIC18F46J11 FAMILY REGISTER 8-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 (ACCESS FA4h) R/W-0 R/W-0 R-0 SSP2IF BCL2IF RC2IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 SSP2IF: Master Synchronous Serial Port 2 Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) ...

Page 117

... TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Note 1: These bits are unimplemented on 28-pin devices. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY R/W-0 R/W-0 R/W-0 TX1IE SSP1IE CCP1IE U = Unimplemented bit, read as ‘0’ ...

Page 118

... PIC18F46J11 FAMILY REGISTER 8-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 (ACCESS FA0h) R/W-0 R/W-0 R/W-0 OSCFIE CM2IE CM1IE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CM2IE: Comparator 2 Interrupt Enable bit ...

Page 119

... Disabled bit 1 TMR3GIE: Timer3 Gate Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 RTCCIE: RTCC Interrupt Enable bit 1 = Enabled 0 = Disabled © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY R/W-0 R/W-0 R/W-0 TX2IE TMR4IE CTMUIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 ...

Page 120

... PIC18F46J11 FAMILY 8.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2, IPR3). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set ...

Page 121

... TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: ECCP2 Interrupt Priority bit 1 = High priority 0 = Low priority © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY U-0 R/W-1 R/W-1 BCL1IP LVDIP — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...

Page 122

... PIC18F46J11 FAMILY REGISTER 8-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 (ACCESS FA5h) R/W-1 R/W-1 R/W-1 SSP2IP BCL2IP RC2IP bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 SSP2IP: Master Synchronous Serial Port 2 Interrupt Priority bit 1 = High priority 0 = Low priority ...

Page 123

... For details on bit operation, see Register 4-1. bit 1 POR: Power-on Reset Status bit For details on bit operation, see Register 4-1. bit 0 BOR: Brown-out Reset Status bit For details on bit operation, see Register 4-1. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY R/W-1 R-1 R Unimplemented bit, read as ‘0’ ...

Page 124

... PIC18F46J11 FAMILY 8.6 INTx Pin Interrupts External interrupts on the INT0, INT1, INT2 and INT3 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. When a valid edge appears on the INTx pin, the corresponding flag bit and INTxIF are set ...

Page 125

... RD PORT Note 1: I/O pins have diode protection © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 9.1 I/O Port Pin Capabilities When developing an application, the capabilities of the port pins must be considered. Outputs on some pins have higher output drive strength than others. Similarly, some pins can tolerate higher than V 9 ...

Page 126

... PIC18F46J11 FAMILY 9.1.3 INTERFACING SYSTEM Though the V of the PIC18F46J11 family is 3.6V, DDMAX these devices are still capable of interfacing with 5V systems, even if the V of the target system is above IH 3.6V. This is accomplished by adding a pull-up resistor to the port pin (Figure 9-2), clearing the LAT bit for that ...

Page 127

... U2OD: USART2 Open-Drain Output Enable bit 1 = Open-drain capability enabled 0 = Open-drain capability disabled bit 0 U1OD: USART1 Open-Drain Output Enable bit 1 = Open-drain capability enabled 0 = Open-drain capability disabled © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ...

Page 128

... PIC18F46J11 FAMILY REGISTER 9-3: ODCON3: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 3 (BANKED F40h) U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-2 Unimplemented: Read as ‘0’ bit 1 SPI2OD: SPI2 Open-Drain Output Enable bit ...

Page 129

... The TRISA register controls the direction of the PORTA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY EXAMPLE 9-2: INITIALIZING PORTA CLRF PORTA ...

Page 130

... PIC18F46J11 FAMILY TABLE 9-3: PORTA I/O SUMMARY TRIS Pin Function Setting RA0/AN0/C1INA/ RA0 1 ULPWU/RP0 0 AN0 1 C1INA 1 ULPWU 1 RP0 1 0 RA1/AN1/C2INA/ RA1 1 PMA7/RP1 0 AN1 1 C2INA 1 (1) PMA7 1 0 RP1 1 0 RA2/AN2/ RA2 0 V -/CV / REF REF C2INB 1 AN2 REF CV x REF C2INB I 0 RA3/AN3/V ...

Page 131

... CVRCON CVREN CVROE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. Note 1: These bits are only available in 44-pin devices. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY I/O I/O Type O DIG LATA<5> data output; not affected by analog input. ...

Page 132

... PIC18F46J11 FAMILY 9.3 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corre- sponding Data Direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i ...

Page 133

... PBADEN is set and digital inputs when PBADEN is cleared. 2: All other pin functions are disabled when ICSP™ or ICD are enabled. 3: This bit is not available on 28-pin devices. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY I/O I/O Type 1 TTL PORTB<0> data input; weak pull-up when RBPU bit is cleared ...

Page 134

... PIC18F46J11 FAMILY TABLE 9-5: PORTB I/O SUMMARY (CONTINUED) TRIS Pin Function Setting RB4/PMA1/ RB4 0 KBI0/RP7 1 (3) PMA1 0 KBI0 1 RP7 1 0 RB5/PMA0/ RB5 0 KBI1/RP8 1 (3) PMA0 0 KBI1 1 RP8 1 0 RB6/KBI2/ RB6 0 PGC/RP9 1 KBI2 1 PGC x RP9 1 0 RB7/KBI3/ RB7 0 PGD/RP10 1 KBI3 1 PGD x x RP10 ...

Page 135

... RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INTCON3 INT2IP INT1IP ADCON0 PCFG7 PCFG6 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 RB5 RB4 RB3 RB2 LATB5 LATB4 ...

Page 136

... PIC18F46J11 FAMILY 9.4 PORTC, TRISC and LATC Registers PORTC is an 8-bit wide, bidirectional port. The corre- sponding Data Direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i ...

Page 137

... C/SMBus input buffer Don’t care (TRIS bit does not affect port direction or is overridden for this option) Note 1: Enhanced PWM output is available only on PIC18F4XJ11 devices. 2: This bit is only available on 44-pin devices. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY (1) I/O I/O Type I ST PORTC< ...

Page 138

... PIC18F46J11 FAMILY TABLE 9-7: PORTC I/O SUMMARY TRIS Pin Function Setting RC5/SDO1/ RC5 1 RP16 0 SDO1 0 RP16 1 0 RC6/PMA5/ RC6 1 TX1/CK1/RP17 0 (2) PMA5 1 0 TX1 0 CK1 1 0 RP17 1 0 RC7/RX1/DT1/ RC7 1 RP18 0 RX1 1 DT1 1 0 RP18 1 0 Legend: DIG = Digital level output; TTL = TTL input buffer Schmitt Trigger input buffer; ANA = Analog level ...

Page 139

... PORTD. All pins on PORTD are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Note POR, these pins are configured as digital inputs. EXAMPLE 9-5: INITIALIZING PORTD ...

Page 140

... PIC18F46J11 FAMILY TABLE 9-9: PORTD I/O SUMMARY TRIS Pin Function Setting RD0/PMD0/ RD0 1 SCL2 0 PMD0 1 0 SCL2 1 0 RD1/PMD1/ RD1 1 SDA2 0 PMD1 1 0 SDA2 1 0 RD2/PMD2/ RD2 1 RP19 0 PMD2 1 0 RP19 1 0 RD3/PMD3/ RD3 1 RP20 0 PMD3 1 0 RP20 1 0 RD4/PMD4/ RD4 ...

Page 141

... LATD6 (1) TRISD TRISD7 TRISD6 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD. Note 1: These registers are not available in 28-pin devices. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY I/O I/O Type I ST PORTD<6> data input. O DIG LATD<6> data output. ...

Page 142

... PORTE, TRISE and LATE Registers Note: PORTE is available only in 44-pin devices. Depending on the particular PIC18F46J11 family device selected, PORTE is implemented in two different ways. For 44-pin devices, PORTE is a 3-bit wide port. Three pins (RE0/AN5/PMRD, RE1/AN6/PMWR and RE2/ AN7/PMCS) are individually configurable as inputs or outputs ...

Page 143

... All PORTD pull-ups are disabled 1 = PORTD pull-ups are enabled for any input pad 2: PORTE Pull-up Enable bit 0 = All PORTE pull-ups are disabled 1 = PORTE pull-ups are enabled for any input pad © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY I/O I/O Type I ST PORTE< ...

Page 144

... I/O pins. The challenge is even greater on low pin count devices similar to the PIC18F46J11 family application that needs to use more than one peripheral multiplexed on single pin, inconvenient workarounds in application code or a complete redesign may be the only option. ...

Page 145

... Note 1: Unless otherwise noted, all inputs use the Schmitt Trigger input buffers. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY with one of the pin selectable peripherals. Programming a given peripheral’s bit field with an appropriate 5-bit value maps the RPn pin with that value to that peripheral ...

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... PIC18F46J11 FAMILY 9.7.3.2 Output Mapping In contrast to inputs, the outputs of the PPS options are mapped on the basis of the pin. In this case, a control register associated with a particular pin dictates the peripheral output to be mapped. The RPORx registers are used to control output mapping. The value of the bit field corresponds to one of the peripherals and that peripheral’ ...

Page 147

... ESD or other external events), a Configuration Mismatch Reset will be triggered. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 9.7.4.3 Configuration Bit Pin Select Lock As an additional level of safety, the device can be con- figured to prevent more than one write session to the RPINRx and RPORx registers. The IOL1WAY (CONFIG3H< ...

Page 148

... PIC18F46J11 FAMILY Choosing the configuration requires the review of all PPSs and their pin assignments, especially those that will not be used in the application. In all cases, unused pin selectable peripherals should be disabled com- pletely. Unused peripherals should have their inputs assigned to an unused RPn pin function. I/O pins with unused RPn functions should be configured with the null peripheral output ...

Page 149

... PERIPHERAL PIN SELECT REGISTERS The PIC18F46J11 family of devices implements a total of 37 registers for remappable peripheral configuration of 44-pin devices. The 28-pin devices have 31 registers for remappable peripheral configuration. REGISTER 9-5: PPSCON: PERIPHERAL PIN SELECT INPUT REGISTER 0 (BANKED EFFh) U-0 U-0 U-0 — ...

Page 150

... PIC18F46J11 FAMILY REGISTER 9-6: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1 (BANKED EE7h) U-0 U-0 U-0 — — — bit 7 Legend: R/W = Readable, Writable if IOLOCK = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 INTR1R< ...

Page 151

... Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 IC1R<4:0>: Assign Input Capture 1 (ECCP1) to the Corresponding RPn Pin bits © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY R/W-1 R/W-1 R/W-1 T0CKR4 T0CKR3 T0CKR2 U = Unimplemented bit, read as ‘0’ ...

Page 152

... PIC18F46J11 FAMILY REGISTER 9-12: RPINR8: PERIPHERAL PIN SELECT INPUT REGISTER 8 (BANKED EEEh) U-0 U-0 U-0 — — — bit 7 Legend: R/W = Readable, Writable if IOLOCK = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 IC2R< ...

Page 153

... Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 SDI2R<4:0>: Assign SPI2 Data Input (SDI2) to the Corresponding RPn Pin bits © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY R/W-1 R/W-1 R/W-1 RX2DT2R4 RX2DT2R3 RX2DT2R2 U = Unimplemented bit, read as ‘0’ ...

Page 154

... PIC18F46J11 FAMILY REGISTER 9-18: RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22 (BANKED EFCh) U-0 U-0 U-0 — — — bit 7 Legend: R/W = Readable, Writable if IOLOCK = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 SCK2R< ...

Page 155

... Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP2R<4:0>: Peripheral Output Function is Assigned to RP2 Output Pin bits (see Table 9-14 for peripheral function numbers) © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY R/W-0 R/W-0 R/W-0 RP0R4 RP0R3 RP0R2 U = Unimplemented bit, read as ‘ ...

Page 156

... PIC18F46J11 FAMILY REGISTER 9-24: RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3 (BANKED EC9h) U-0 U-0 U-0 — — — bit 7 Legend: R/W = Readable, Writable if IOLOCK = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP3R< ...

Page 157

... Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP8R<4:0>: Peripheral Output Function is Assigned to RP8 Output Pin bits (see Table 9-14 for peripheral function numbers) © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY R/W-0 R/W-0 R/W-0 RP6R4 RP6R3 RP6R2 U = Unimplemented bit, read as ‘ ...

Page 158

... PIC18F46J11 FAMILY REGISTER 9-30: RPOR9: PERIPHERAL PIN SELECT OUTPUT REGISTER 9 (BANKED ECFh) U-0 U-0 U-0 — — — bit 7 Legend: R/W = Readable, Writable if IOLOCK = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP9R< ...

Page 159

... Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP14R<4:0>: Peripheral Output Function is Assigned to RP14 Output Pin bits (see Table 9-14 for peripheral function numbers) © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY R/W-0 R/W-0 R/W-0 RP12R4 RP12R3 RP12R2 U = Unimplemented bit, read as ‘ ...

Page 160

... PIC18F46J11 FAMILY REGISTER 9-36: RPOR15: PERIPHERAL PIN SELECT OUTPUT REGISTER 15 (BANKED ED5h) U-0 U-0 U-0 — — — bit 7 Legend: R/W = Readable, Writable if IOLOCK = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP15R< ...

Page 161

... Unimplemented: Read as ‘0’ bit 4-0 RP20R<4:0>: Peripheral Output Function is Assigned to RP20 Output Pin bits (see Table 9-14 for peripheral function numbers) Note 1: RP20 pins are not available on 28-pin devices. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY R/W-0 R/W-0 R/W-0 RP18R4 RP18R3 RP18R2 U = Unimplemented bit, read as ‘ ...

Page 162

... PIC18F46J11 FAMILY REGISTER 9-42: RPOR21: PERIPHERAL PIN SELECT OUTPUT REGISTER 21 (BANKED EDBh) U-0 U-0 U-0 — — — bit 7 Legend: R/W = Readable, Writable if IOLOCK = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP21R< ...

Page 163

... Unimplemented: Read as ‘0’ bit 4-0 RP24R<4:0>: Peripheral Output Function is Assigned to RP24 Output Pin bits (see Table 9-14 for peripheral function numbers) Note 1: RP24 pins are not available on 28-pin devices. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY R/W-0 R/W-0 R/W-0 RP24R4 RP24R3 RP24R2 U = Unimplemented bit, read as ‘ ...

Page 164

... PIC18F46J11 FAMILY NOTES: DS39932C-page 164 © 2009 Microchip Technology Inc. ...

Page 165

... Slave Port (PSP). FIGURE 10-1: PMP MODULE OVERVIEW PIC18 Parallel Master Port © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Key features of the PMP module are: • bits of Addressing when Using Data/Address Multiplexing • Programmable Address Lines • One Chip Select Line • ...

Page 166

... PIC18F46J11 FAMILY 10.1 Module Registers The PMP module has a total of 14 Special Function Registers (SFRs) for its operation, plus one additional register to set configuration options. Of these, eight registers are used for control and six are used for PMP data transfer. 10.1.1 ...

Page 167

... Read/write strobe active-high (PMRD/PMWR Read/write strobe active-low (PMRD/PMWR) Note 1: This register is only available in 44-pin devices. 2: These bits have no effect when their corresponding pins are used as address lines. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY (2) (2) U-0 R/W-0 — CS1P U = Unimplemented bit, read as ‘0’ ...

Page 168

... PIC18F46J11 FAMILY REGISTER 10-3: PMMODEH: PARALLEL PORT MODE REGISTER HIGH BYTE (BANKED F5Dh) R-0 R/W-0 R/W-0 BUSY IRQM1 IRQM0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 BUSY: Busy bit (Master mode only Port is busy 0 = Port is not busy bit 6-5 IRQM< ...

Page 169

... Wait Note 1: This register is only available in 44-pin devices. 2: WAITBx and WAITEx bits are ignored whenever WAITM<3:0> = 0000. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY R/W-0 R/W-0 WAITM2 WAITM1 WAITM0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ; multiplexed address phase ...

Page 170

... PIC18F46J11 FAMILY REGISTER 10-5: PMEH: PARALLEL PORT ENABLE REGISTER HIGH BYTE (BANKED F57h) U-0 R/W-0 U-0 — PTEN14 — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 Unimplemented: Read as ‘0’ bit 6 PTEN14: PMCS1 Port Enable bit ...

Page 171

... OB3E:OB0E: Output Buffer x Status Empty bits 1 = Output buffer is empty (writing data to the buffer will clear this bit Output buffer contains data that has not been transmitted Note 1: This register is only available in 44-pin devices. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY U-0 R-0 R-0 — IB3F IB2F U = Unimplemented bit, read as ‘ ...

Page 172

... PIC18F46J11 FAMILY 10.1.2 DATA REGISTERS The PMP module uses eight registers for transferring data into and out of the microcontroller. They are arranged as four pairs to allow the option of 16-bit data operations: • PMDIN1H and PMDIN1L • PMDIN2H and PMDIN2L • PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L • ...

Page 173

... Bit is set bit 7-0 Parallel Master Port Address: Low Byte<7:0> bits Note 1: In Enhanced Slave mode, PMADDRL functions as PMDOUT1L, one of the Output Data Buffer registers. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY (1) R/W-0 R/W-0 R/W-0 Parallel Master Port Address High Byte<13:8> ...

Page 174

... PIC18F46J11 FAMILY 10.2 Slave Port Modes The primary mode of operation for the module is configured using the MODE<1:0> PMMODEH register. The setting affects whether the module acts as a slave or a master, and it determines the usage of the control pins. 10.2.1 LEGACY MODE (PSP) ...

Page 175

... PMRD PMD<7:0> IBF OBE PMPIF © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 10.2.3 READ FROM SLAVE PORT When chip select is active and a read strobe occurs (PMCS = 1 and PMRD = 1), the data from the PMDOUT1L register (PMDOUT1L<7:0>) is presented onto PMD<7:0>. Figure 10-4 provides the timing for the control signals in Read mode ...

Page 176

... PIC18F46J11 FAMILY 10.2.4 BUFFERED PARALLEL SLAVE PORT MODE Buffered Parallel Slave Port mode is functionally identical to the legacy PSP mode with one exception, the implementation of 4-level read and write buffers. Buffered PSP mode is enabled by setting the INCM bits in the PMMODEH register. If the INCM<1:0> bits are set to ‘ ...

Page 177

... ADDR<1:0>. Table 10-1 provides the corresponding FIGURE 10-7: PARALLEL SLAVE PORT READ WAVEFORMS PMCS PMWR PMRD PMD<7:0> PMA<1:0> OBE PMPIF © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY TABLE 10-1: SLAVE MODE BUFFER ADDRESSING Output PMA<1:0> Register (Buffer) PMDOUT1L (0) 00 PMDOUT1H (1) 01 ...

Page 178

... PIC18F46J11 FAMILY 10.2.5.2 WRITE TO SLAVE PORT When chip select is active and a write strobe occurs (PMCS = 1 and PMWR = 1), the data from PMD<7:0> is captured into one of the four input buffer bytes. Which byte is written depends on the 2-bit address placed on ADDRL<1:0>. Table 10-1 provides the corresponding input registers and their associated address ...

Page 179

... Configuration is controlled by separate bits in the PMCONL register. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Note that the polarity of control signals that share the same output pin (for example, PMWR and PMENB) are controlled by the same bit; the configuration depends on which Master Port mode is being used ...

Page 180

... PIC18F46J11 FAMILY FIGURE 10-9: DEMULTIPLEXED ADDRESSING MODE (SEPARATE READ AND WRITE STROBES WITH CHIP SELECT) PIC18F FIGURE 10-10: PARTIALLY MULTIPLEXED ADDRESSING MODE (SEPARATE READ AND WRITE STROBES WITH CHIP SELECT) PIC18F FIGURE 10-11: FULLY MULTIPLEXED ADDRESSING MODE (SEPARATE READ AND WRITE ...

Page 181

... PMDIN1L register, and the second read data is placed into the PMDIN1H. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Note that the read data obtained from the PMDIN1L register is actually the read value from the previous read operation. Hence, the first user read will be a dummy read to initiate the first bus read and fill the read register ...

Page 182

... PIC18F46J11 FAMILY 10.3.11 MASTER MODE TIMING This section contains a number of timing examples that represent the common Master mode configuration options. These options vary from 8-bit to 16-bit data, fully demultiplexed to fully multiplexed address and Wait states. FIGURE 10-12: READ AND WRITE TIMING, 8-BIT DATA, DEMULTIPLEXED ADDRESS ...

Page 183

... PMCS1 PMD<7:0> Address<7:0> PMWR PMRD PMALL PMPIF BUSY WAITB<1:0> FIGURE 10-17: READ TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS, ENABLE STROBE PMCS1 PMD<7:0> Address<7:0> PMRD/PMWR PMENB PMALL PMPIF BUSY © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Data Data WAITE<1:0> WAITM<3:0> = 0010 Data ...

Page 184

... PIC18F46J11 FAMILY FIGURE 10-18: WRITE TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS, ENABLE STROBE PMCS1 PMD<7:0> Address<7:0> PMRD/PMWR PMENB PMALL PMPIF BUSY FIGURE 10-19: READ TIMING, 8-BIT DATA, FULLY MULTIPLEXED 16-BIT ADDRESS PMCS1 Address<7:0> PMD<7:0> PMWR PMRD PMALL PMALH PMPIF BUSY FIGURE 10-20: ...

Page 185

... WRITE TIMING, 16-BIT DATA, DEMULTIPLEXED ADDRESS PMCS1 PMD<7:0> PMA<7:0> PMWR PMRD PMBE PMPIF BUSY FIGURE 10-23: READ TIMING, 16-BIT MULTIPLEXED DATA, PARTIALLY MULTIPLEXED ADDRESS PMCS1 PMD<7:0> Address<7:0> PMWR PMRD PMBE PMALL PMPIF BUSY © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY LSB MSB LSB MSB LSB MSB ...

Page 186

... PIC18F46J11 FAMILY FIGURE 10-24: WRITE TIMING, 16-BIT MULTIPLEXED DATA, PARTIALLY MULTIPLEXED ADDRESS PMCS1 PMD<7:0> Address<7:0> PMWR PMRD PMBE PMALL PMPIF BUSY FIGURE 10-25: READ TIMING, 16-BIT MULTIPLEXED DATA, FULLY MULTIPLEXED 16-BIT ADDRESS PMCS1 PMD<7:0> Address<7:0> PMWR PMRD PMBE PMALH PMALL PMPIF ...

Page 187

... PIC18F PMD<7:0> PMALL PMCS PMRD PMWR © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 10.4.1 MULTIPLEXED MEMORY OR PERIPHERAL Figure 10-27 demonstrates the hookup of a memory or another addressable peripheral in Full Multiplex mode. Consequently, this mode achieves the best pin saving from the microcontroller perspective. However, for this configuration, there needs to be some external latches to maintain the address ...

Page 188

... PIC18F46J11 FAMILY 10.4.3 PARALLEL EEPROM EXAMPLE Figure 10-30 provides an example connecting parallel EEPROM to the PMP. Figure 10-31 demonstrates a slight variation to this, configuring the connection for 16-bit data from a single EEPROM. FIGURE 10-30: PARALLEL EEPROM EXAMPLE (UP TO 15-BIT ADDRESS, 8-BIT DATA) PIC18F PMA< ...

Page 189

... The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different functions determined by the module’s operating mode. 2: These bits and/or registers are only available in 44-pin devices. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 ...

Page 190

... PIC18F46J11 FAMILY NOTES: DS39932C-page 190 © 2009 Microchip Technology Inc. ...

Page 191

... Prescale value 000 = 1:2 Prescale value © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY The T0CON register (Register 11-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. Figure 11-1 provides a simplified block diagram of the Timer0 module in 8-bit mode ...

Page 192

... PIC18F46J11 FAMILY 11.1 Timer0 Operation Timer0 can operate as either a timer or a counter. The mode is selected with the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on every clock by default unless a different prescaler value is selected (see Section 11.3 “Prescaler”). If the TMR0 register is written to, the increment is inhibited for the following two instruction cycles ...

Page 193

... GIE/GIEH PEIE/GIEL TMR0IE T0CON TMR0ON T08BIT Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Timer0. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY 11.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “on-the-fly” during program execution ...

Page 194

... PIC18F46J11 FAMILY NOTES: DS39932C-page 194 © 2009 Microchip Technology Inc. ...

Page 195

... ECCP capture/compare OSC features. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY Figure 12-1 displays a simplified block diagram of the Timer1 module. The module incorporates its own low-power oscillator to provide an additional clocking option. The Timer1 oscillator can also be used as a low-power clock source for the microcontroller in power-managed operation ...

Page 196

... PIC18F46J11 FAMILY 12.1 Timer1 Gate Control Register The Timer1 Gate Control register displayed in Register 12-2, is used to control the Timer1 gate. REGISTER 12-2: T1GCON: TIMER1 GATE CONTROL REGISTER (F9Ah) R/W-0 R/W-0 R/W-0 TMR1GE T1GPOL T1GTM bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘ ...

Page 197

... ECCP1 and ECCP2 both use Timer3 (capture/compare) and Timer4 (PWM ECCP1 uses Timer1 (compare/capture) and Timer2 (PWM); ECCP2 uses Timer3 (capture/compare) and Timer4 (PWM ECCP1 and ECCP2 both use Timer1 (capture/compare) and Timer2 (PWM) © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY R-0 U-0 U-0 T1RUN — ...

Page 198

... PIC18F46J11 FAMILY 12.2 Timer1 Operation The Timer1 module is an 8-bit or 16-bit incrementing counter, which is accessed TMR1H:TMR1L register pair. When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module ...

Page 199

... T1OSO/T1CKI OUT T1OSC T1OSI EN T1OSCEN T1CKI Note 1: ST Buffer is high-speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. © 2009 Microchip Technology Inc. PIC18F46J11 FAMILY T1GSPM T1G_IN 0 Single Pulse Acq. Control T1GGO/T1DONE CK R TMR1ON ...

Page 200

... PIC18F46J11 FAMILY 12.4 Timer1 16-Bit Read/Write Mode Timer1 can be configured for 16-bit reads and writes. When the RD16 control bit (T1CON<1>) is set, the address for TMR1H is mapped to a buffer register for the high byte of Timer1. A read from TMR1L loads the contents of the high byte of Timer1 into the Timer1 High Byte Buffer register ...

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