PIC18F1330-I/SO Microchip Technology, PIC18F1330-I/SO Datasheet - Page 184

• Manufacturer Part Number: PIC18F1330-I/SO
• Description: IC PIC MCU FLASH 4KX16 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F1330-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 18-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 128 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Operating Supply Voltage: 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4-ch x 10-bit
• Package: 18SOIC W
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F1230/1330
18.5
In many applications, the ability to detect a drop below
a particular threshold is desirable.
For general battery applications, Figure 18-3 shows a
possible voltage curve. Over time, the device voltage
decreases. When the device voltage reaches voltage
V
interrupt could cause the execution of an ISR, which
would allow the application to perform “housekeeping
tasks” and perform a controlled shutdown before the
device voltage exits the valid operating range at T
The LVD, thus, would give the application a time win-
dow, represented by the difference between T
to safely exit.
FIGURE 18-3:
TABLE 18-1:
DS39758C-page 182
LVDCON
INTCON
PIR2
PIE2
IPR2
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the LVD module.
A
, the LVD logic generates an interrupt at time T
Name
Legend:
V
V
A
B
Applications
V
V
GIE/GIEH PEIE/GIEL TMR0IE
OSCFIE
OSCFIP
OSCFIF
A
B
Bit 7
= LVD trip point
= Minimum valid device
REGISTERS ASSOCIATED WITH LOW-VOLTAGE DETECT MODULE
—
operating voltage
TYPICAL LOW-VOLTAGE
DETECT APPLICATION
Time
Bit 6
—
—
—
—
T
A
T
B
IRVST
Bit 5
—
—
—
Advance Information
A
and T
A
. The
LVDEN
INT0IE
B
B
EEIE
EEIP
Bit 4
EEIF
.
,
18.6
When enabled, the LVD circuitry continues to operate
during Sleep. If the device voltage crosses the trip
point, the LVDIF bit will be set and the device will wake-
up from Sleep. Device execution will continue from the
interrupt vector address if interrupts have been globally
enabled.
18.7
A device Reset forces all registers to their Reset state.
This forces the LVD module to be turned off.
LVDL3
RBIE
Bit 3
—
—
—
Operation During Sleep
Effects of a Reset
TMR0IF
LVDL2
LVDIF
LVDIE
LVDIP
Bit 2
LVDL1
INT0IF
© 2007 Microchip Technology Inc.
Bit 1
—
—
—
LVDL0
RBIF
Bit 0
—
—
—
on Page:
Values
Reset
42
41
43
43
43