PIC18F1330-I/SO Microchip Technology, PIC18F1330-I/SO Datasheet
PIC18F1330-I/SO
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PIC18F1330-I/SO Summary of contents
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... Microcontrollers with nanoWatt Technology, High Performance PWM and A/D © 2007 Microchip Technology Inc. PIC18F1230/1330 18/20/28-Pin Enhanced Flash Advance Information Data Sheet DS39758C ...
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... Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Two-Speed Oscillator Start-up Program Memory Device Flash # Single-Word (bytes) Instructions PIC18F1230 4096 2048 PIC18F1330 8192 4096 © 2007 Microchip Technology Inc. PIC18F1230/1330 Peripheral Highlights: • High-Current Sink/Source 25 mA/25 mA • Programmable External Interrupts • Four Input Change Interrupts • Enhanced Addressable USART module: - Supports RS-485, RS-232 and LIN 1 ...
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... RB7/PWM5/PGD 7 12 RB6/PWM4/PGC 8 11 RB5/PWM3 9 10 RB4/PWM2 1 20 RB3/INT3/KBI3/CMP1/T1OSI 2 19 RB2/INT2/KBI2/CMP2/T1OSO 3 18 RA7/OSC1/CLKI/T1OSI 4 17 RA6/OSC2/CLKO/T1OSO RB7/PWM5/PGD RB6/PWM4/PGC 9 RB5/PWM3 12 10 RB4/PWM2 11 Advance Information (1) (1) (1) /T1CKI (1) (2) /FLTA (1) (1) /T1CKI /AN3 (1) (1) (1) /T1CKI (1) (2) /FLTA (1) (1) /T1CKI /AN3 © 2007 Microchip Technology Inc. ...
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... Placement of T1OSI and T1OSO/T1CKI depends on the value of Configuration bit, T1OSCMX, of CONFIG3H. 2: Placement of FLTA depends on the value of Configuration bit, FLTAMX, of CONFIG3H recommended that the user connect the center metal pad for this device package to the ground. © 2007 Microchip Technology Inc. PIC18F1230/1330 ...
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... Appendix E: Migration from Mid-Range TO Enhanced Devices ........................................................................................................ 297 Appendix F: Migration from High-End to Enhanced Devices ............................................................................................................. 297 Index ................................................................................................................................................................................................. 299 The Microchip Web Site ..................................................................................................................................................................... 307 Customer Change Notification Service .............................................................................................................................................. 307 Customer Support .............................................................................................................................................................................. 307 Reader Response .............................................................................................................................................................................. 308 PIC18F1230/1330 Product Identification System .............................................................................................................................. 309 DS39758C-page 4 Advance Information © 2007 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2007 Microchip Technology Inc. PIC18F1230/1330 Advance Information DS39758C-page 5 ...
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... PIC18F1230/1330 NOTES: DS39758C-page 6 Advance Information © 2007 Microchip Technology Inc. ...
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... DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC18F1230 • PIC18F1330 This family offers the advantages of all PIC18 micro- controllers – namely, high computational performance at an economical price – with the addition of high- endurance Enhanced Flash program memory. On top of ...
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... Like all Microchip PIC18 devices, members of the PIC18F1230/1330 family are available as both stan- dard and low-voltage devices. Standard devices with Enhanced Flash memory, designated with an “F” in the part number (such as PIC18F1330), accommodate an operating V range of 4.2V to 5.5V. Low-voltage DD parts, designated by “LF” (such as PIC18LF1330), ...
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... Stack Underflow (PWRT, OST), MCLR (optional), WDT Yes Yes 75 Instructions; 83 with Extended Instruction Set enabled 18-Pin PDIP 18-Pin SOIC 20-Pin SSOP 28-Pin QFN Advance Information PIC18F1330 DC – 40 MHz 8192 4096 256 128 17 Ports Channels Enhanced USART 4 Input Channels POR, BOR, RESET Instruction, ...
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... PIC18F1230/1330 FIGURE 1-1: PIC18F1230/1330 (18-PIN) BLOCK DIAGRAM Table Pointer <2> 21 inc/dec logic PCLATU Address Latch Program Memory (4 Kbytes) PIC18F1230 (8 Kbytes) PIC18F1330 Data Latch 16 Table Latch 8 ROM Latch Instruction Register Instruction Decode & Control (2) Power-up OSC1 Timing (2) Generation OSC2 Oscillator Start-up Timer ...
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... ST = Schmitt Trigger input with CMOS levels O = Output Note 1: Placement of FLTA depends on the value of Configuration bit, FLTAMX, of CONFIG3H. 2: Placement of T1OSI and T1OSO/T1CKI depends on the value of Configuration bit, T1OSCMX, of CONFIG3H. © 2007 Microchip Technology Inc. PIC18F1230/1330 Pin Buffer Type Type QFN 1 Master Clear (input), programming voltage (input) or Fault detect input ...
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... TTL Digital I/ EUSART asynchronous receive. I/O ST EUSART synchronous data. 28 I/O TTL Digital I/ Timer0 external clock input. I Analog Analog input 2. I Analog A/D reference voltage (high) input. CMOS = CMOS compatible input or output I = Input P = Power Advance Information Description © 2007 Microchip Technology Inc. ...
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... ST = Schmitt Trigger input with CMOS levels O = Output Note 1: Placement of FLTA depends on the value of Configuration bit, FLTAMX, of CONFIG3H. 2: Placement of T1OSI and T1OSO/T1CKI depends on the value of Configuration bit, T1OSCMX, of CONFIG3H. © 2007 Microchip Technology Inc. PIC18F1230/1330 Pin Buffer Type Type QFN PORTB is a bidirectional I/O port. ...
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... Positive supply for logic and I/O pins — Ground reference for A/D Converter module — Positive supply for A/D Converter module — — No Connect. 11, 14, 18, 22, 25 CMOS = CMOS compatible input or output I = Input P = Power Advance Information Description © 2007 Microchip Technology Inc. ...
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... The oscillator design requires the use of a parallel cut crystal. Note: Use of a series cut crystal may give a fre- quency out of the crystal manufacturer’s specifications. © 2007 Microchip Technology Inc. PIC18F1230/1330 FIGURE 2-1: (1) C1 (1) C2 Note 1: See Table 2-1 and Table 2-2 for initial values of C1 and C2 ...
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... Clock from Ext. System Advance Information EXTERNAL CLOCK INPUT OPERATION (HS OSCILLATOR CONFIGURATION) OSC1 PIC18FXXXX (HS Mode) Open OSC2 EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION) OSC1/CLKI PIC18FXXXX /4 OSC2/CLKO OSC EXTERNAL CLOCK INPUT OPERATION (ECIO CONFIGURATION) OSC1/CLKI PIC18FXXXX I/O (OSC2) RA6 © 2007 Microchip Technology Inc. ...
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... Recommended values: 3 kΩ ≤ R ≤ 100 kΩ EXT C > EXT © 2007 Microchip Technology Inc. PIC18F1230/1330 2.5 PLL Frequency Multiplier A Phase Locked Loop (PLL) circuit is provided as an option for users who wish to use a lower frequency oscillator circuit or to clock the device up to its highest rated frequency from a crystal oscillator ...
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... Two compensation techniques are discussed in Section 2.6.5.1 EUSART” and Section 2.6.5.2 “Compensating with the Timers”, but other techniques may be used. Advance Information or temperature changes, which can “Compensating with the © 2007 Microchip Technology Inc. ...
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... OSCTUNE to reduce the clock frequency. On the other hand, errors in data may suggest that the clock speed is too low; to compensate, increment OSCTUNE to increase the clock frequency. © 2007 Microchip Technology Inc. PIC18F1230/1330 R/W-0 R/W-0 R/W-0 TUN4 ...
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... OSCTUNE<7> Advance Information LP, XT, HS, RC, EC Peripherals T1OSC Internal Oscillator CPU IDLEN Clock Control FOSC3:FOSC0 OSCCON<1:0> Clock Source Option for Other Modules WDT, PWRT, FSCM and Two-Speed Start-up © 2007 Microchip Technology Inc. ...
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... INTRC is providing the clock or the internal oscillator block has just started and is not yet stable. © 2007 Microchip Technology Inc. PIC18F1230/1330 The IDLEN bit determines if the device goes into Sleep mode or one of the Idle modes when the SLEEP instruction is executed ...
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... Source selected by the INTSRC bit (OSCTUNE<7>), see text. 3: Default output frequency of INTOSC on Reset. DS39758C-page 22 (1) R/W-0 R R-0 IRCF0 OSTS IOFS U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) (1) Advance Information R/W-0 R/W-0 SCS1 SCS0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... Feedback inverter disabled at quiescent voltage level Note: See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset. © 2007 Microchip Technology Inc. PIC18F1230/1330 time clock. Other features may be operating that do not require a device clock source (i.e., INTx pins and others). Peripherals that may add significant current consumption are listed in Section 22.0 “ ...
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... PIC18F1230/1330 NOTES: DS39758C-page 24 Advance Information © 2007 Microchip Technology Inc. ...
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... Note 1: IDLEN reflects its value when the SLEEP instruction is executed. 2: Includes INTOSC and INTOSC postscaler, as well as the INTRC source. © 2007 Microchip Technology Inc. PIC18F1230/1330 3.1.1 CLOCK SOURCES The SCS1:SCS0 bits allow the selection of one of three clock sources for power-managed modes. They are: power • ...
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... When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run. Advance Information © 2007 Microchip Technology Inc. ...
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... PRI_RUN and RC_RUN modes during execution. However, a clock switch delay will occur during entry to and exit from RC_RUN mode. Therefore, if the primary clock source is the internal oscillator block, the use of RC_RUN mode is not recommended. © 2007 Microchip Technology Inc. PIC18F1230/1330 n-1 ...
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... The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled n-1 n (1) Clock Transition OSC OST (1) T (1) T PLL 1 2 n-1 n Clock (2) Transition PC OSTS bit Set ; (approx). These intervals are not shown to scale. PLL . OSC Advance Information © 2007 Microchip Technology Inc. ...
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... (approx). These intervals are not shown to scale. OST OSC PLL © 2007 Microchip Technology Inc. PIC18F1230/1330 3.4 Idle Modes The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to a ‘ ...
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... SEC_IDLE mode will not occur. If the Timer1 oscillator is enabled but not yet running, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result CSD PC Advance Information © 2007 Microchip Technology Inc. ...
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... INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. © 2007 Microchip Technology Inc. PIC18F1230/1330 On all exits from Idle or Sleep modes by interrupt, code execution branches to the interrupt vector if the GIE/ GIEH bit (INTCON< ...
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... OST (3) LP, XT HSPLL T OST EC CSD (1) INTOSC T IOBST is the PLL Lock-out Timer (parameter F12 (parameter 39), the INTOSC stabilization period. IOBST Advance Information Clock Ready Status Bit (OSCCON) OSTS (1) IOFS (3) ( OSTS rc IOFS (4) ( OSTS rc (1) IOFS ( OSTS rc (1) (4) IOFS © 2007 Microchip Technology Inc. ...
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... Ripple Counter Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin. 2: See Table 4-2 for time-out situations. © 2007 Microchip Technology Inc. PIC18F1230/1330 A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 4-1. ...
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... Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to ‘1’ by software immediately after a Power-on Reset). DS39758C-page 34 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) Advance Information (2) R/W-0 R/W-0 POR BOR bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... Power-on Reset occurs; it does not change for any other Reset event. POR is not reset to ‘1’ by any hard- ware event. To capture multiple events, the user manually resets the bit to ‘1’ in software following any Power-on Reset. © 2007 Microchip Technology Inc. PIC18F1230/1330 FIGURE 4- ...
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... BOR disabled; must be enabled by reprogramming the Configuration bits. BOR enabled in software; operation controlled by SBOREN. BOR enabled in hardware in Run and Idle modes, disabled during Sleep mode. BOR enabled in hardware; must be disabled by reprogramming the Configuration bits. Advance Information © 2007 Microchip Technology Inc. ...
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... Note (65.5 ms) is the nominal Power-up Timer (PWRT) delay the nominal time required for the PLL to lock. © 2007 Microchip Technology Inc. PIC18F1230/1330 4.5.3 PLL LOCK TIME-OUT With the PLL enabled in its PLL mode, the time-out sequence following a Power-on Reset is slightly different from other oscillator modes ...
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... INTERNAL RESET FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET DS39758C-page 38 T PWRT T OST T PWRT T T PWRT T Advance Information , V RISE < PWRT ): CASE 1 DD OST ): CASE 2 DD OST © 2007 Microchip Technology Inc. ...
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... TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 clock cycles. OST ≈ max. First three stages of the PWRT timer. T PLL © 2007 Microchip Technology Inc. PIC18F1230/1330 , V RISE > PWRT T OST T PWRT T OST ...
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... Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups. RCON Register SBOREN 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h ( (1) ( Advance Information STKPTR Register POR BOR STKFUL STKUNF © 2007 Microchip Technology Inc. ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as ‘0’. 6: Reset condition of PWMEN bits depends on the PWMPIN Configuration bit of CONFIG3L. © 2007 Microchip Technology Inc. PIC18F1230/1330 MCLR Resets, Power-on Reset, ...
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... Microchip Technology Inc. ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as ‘0’. 6: Reset condition of PWMEN bits depends on the PWMPIN Configuration bit of CONFIG3L. © 2007 Microchip Technology Inc. PIC18F1230/1330 MCLR Resets, Power-on Reset, ...
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... Advance Information Wake-up via WDT or Interrupt ---- uuuu (6) (6) -uuu -uuu (6) (6) -uuu -uuu uuuu u-uu uuuu uuuu --uu uuuu --uu uuuu uuuu uuuu (5) (5) uuuu uuuu © 2007 Microchip Technology Inc. ...
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... NOP instruction). The PIC18F1230 has 4 Kbytes of Flash memory and can store up to 2,048 single-word instructions. The PIC18F1330 has 8 Kbytes of Flash memory and can store up to 4,096 single-word instructions. PIC18 devices have two interrupt vectors. The Reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h ...
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... The user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption. Return Address Stack <20:0> 11111 11110 11101 TOSL 34h 00011 001A34h 00010 Top-of-Stack 000D58h 00001 00000 Advance Information can return these values to Stack Pointer STKPTR<4:0> 00010 © 2007 Microchip Technology Inc. ...
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... SP4:SP0: Stack Pointer Location bits Note 1: Bit 7 and bit 6 are cleared by user software POR. © 2007 Microchip Technology Inc. PIC18F1230/1330 When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero ...
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... Data is transferred to or from program memory one byte at a time. Table read and table write operations are discussed further in Section 6.1 “Table Reads and Table Writes”. Advance Information COMPUTED GOTO USING AN OFFSET VALUE OFFSET, W TABLE PCL nnh nnh nnh © 2007 Microchip Technology Inc. ...
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... Instruction @ address SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. © 2007 Microchip Technology Inc. PIC18F1230/1330 5.2.2 INSTRUCTION FLOW/PIPELINING An “ ...
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... REG1 ; is RAM location 0? REG1, REG2 ; Yes, execute this word ; 2nd word of instruction REG3 ; continue code Advance Information address embedded into the Word Address ↓ 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h © 2007 Microchip Technology Inc. ...
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... SFRs and the lower portion of GPR Bank 0 without using the BSR. Section 5.3.2 “Access Bank” provides a detailed description of the Access RAM. © 2007 Microchip Technology Inc. PIC18F1230/1330 5.3.1 BANK SELECT REGISTER (BSR) Large areas of data memory require an efficient addressing scheme to make rapid access to any address possible ...
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... RAM (from Bank 0). The second 128 bytes are Special Function Registers (from Bank 15). When The BSR specifies the Bank used by the instruction. Access Bank 00h Access RAM Low 7Fh 80h Access RAM High (SFRs) FFh © 2007 Microchip Technology Inc. ...
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... Access RAM bit (the ‘a’ parameter in the instruction). When ‘a’ is equal to ‘1’, the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When ‘a’ is ‘0’, © 2007 Microchip Technology Inc. PIC18F1230/1330 7 Data Memory ...
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... F91h PDC0L F90h PDC0H F8Fh PDC1L F8Eh PDC1H F8Dh PDC2L F8Ch PDC2H F8Bh FLTCONFIG F8Ah LATB F89h LATA F88h SEVTCMPL (1) F87h SEVTCMPH F86h PWMCON0 F85h PWMCON1 F84h DTCON F83h OVDCOND F82h OVDCONS F81h PORTB F80h PORTA © 2007 Microchip Technology Inc. ...
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... Bit 7 and bit 6 are cleared by user software POR. 6: Reset condition of PWMEN bits depends on the PWMPIN Configuration bit of CONFIG3L. 7: This bit has no effect if the Configuration bit, WDTEN, is enabled. © 2007 Microchip Technology Inc. PIC18F1230/1330 Bit 4 Bit 3 Bit 2 — Top-of-Stack Upper Byte (TOS<20:16>) — ...
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... CMP0IP TMR1IP -111 1111 43, 96 CMP0IF TMR1IF -000 0000 43, 92 CMP0IE TMR1IE -000 0000 43, 94 TUN1 TUN0 00-0 0000 43, 19 PTMOD1 PTMOD0 0000 0000 43, 116 — — 00-- ---- 43, 116 © 2007 Microchip Technology Inc. ...
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... When disabled, these bits read as ‘0’. 5: Bit 7 and bit 6 are cleared by user software POR. 6: Reset condition of PWMEN bits depends on the PWMPIN Configuration bit of CONFIG3L. 7: This bit has no effect if the Configuration bit, WDTEN, is enabled. © 2007 Microchip Technology Inc. PIC18F1230/1330 Bit 4 Bit 3 Bit 2 — — ...
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... Table 21-2 and Table 21-3. Note: The C and DC bits operate as the borrow and digit borrow bits, respectively, in subtraction. R/W-x R/W-x R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Advance Information R/W-x R/W-x (1) ( bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... Purpose Register File” location in the Access Bank (Section 5.3.2 “Access Bank”) as the data source for the instruction. © 2007 Microchip Technology Inc. PIC18F1230/1330 The Access RAM bit ‘a’ determines how the address is interpreted. When ‘a’ is ‘1’, the contents of the BSR (Section 5.3.1 “ ...
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... FSRnH register. On the other hand, results of these operations do not change the value of any flags in the STATUS register (e.g OV, etc.). ADDWF, INDF1, 1 FSR1H:FSR1L Advance Information 000h Bank 0 100h Bank 1 200h Bank 2 300h 0 Bank 3 through Bank 13 E00h Bank 14 F00h Bank 15 FFFh Data Memory © 2007 Microchip Technology Inc. ...
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... The SFR map remains the same. Core PIC18 instructions can still operate in both Direct and Indirect Addressing mode; inherent and literal instructions do not change at all. Indirect Addressing with FSR0 and FSR1 also remains unchanged. © 2007 Microchip Technology Inc. PIC18F1230/1330 5.5.1 INDEXED ADDRESSING WITH LITERAL OFFSET ...
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... Data Memory 000h Bank 0 080h 100h Bank 1 through Bank 14 F00h Bank 15 F80h SFRs FFFh Data Memory Advance Information 00h 60h 80h Valid range for ‘f’ FFh Access RAM 001001da ffffffff FSR2H FSR2L BSR 00000000 001001da ffffffff © 2007 Microchip Technology Inc. ...
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... Bank 0 addresses below 5Fh can still be addressed F80h by using the BSR. FFFh © 2007 Microchip Technology Inc. PIC18F1230/1330 Remapping of the Access Bank applies only to operations using the Indexed Literal Offset Addressing mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue to use Direct Addressing as before. ...
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... PIC18F1230/1330 NOTES: DS39758C-page 64 Advance Information © 2007 Microchip Technology Inc. ...
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... TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. © 2007 Microchip Technology Inc. PIC18F1230/1330 6.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
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... The WR control bit initiates write operations. The bit cannot be cleared, only set, in software cleared in hardware at the completion of the write operation. Note: The EEIF interrupt flag bit (PIR2<4>) is set when the write is complete. It must be cleared in software. When set, Advance Information Table Latch (8-bit) TABLAT © 2007 Microchip Technology Inc. ...
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... RD bit cannot be set when EEPGD = 1 or CFGS = 1 Does not initiate an EEPROM read Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. © 2007 Microchip Technology Inc. PIC18F1230/1330 R/W-0 R/W-x R/W-0 ...
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... Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write TBLPTRH 8 7 TBLPTR<21:6> TABLE READ – TBLPTR<21:0> Advance Information of the Table Pointer register TBLPTRL 0 TABLE WRITE TBLPTR<5:0> © 2007 Microchip Technology Inc. ...
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... TBLRD*+ MOVF TABLAT, W MOVWF WORD_ODD © 2007 Microchip Technology Inc. PIC18F1230/1330 The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 6-4 shows the interface between the internal program memory and the TABLAT ...
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... TBLPTR with the base ; address of the memory block ; point to Flash program memory ; access Flash program memory ; enable write to memory ; enable Row Erase operation ; disable interrupts ; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts Advance Information © 2007 Microchip Technology Inc. ...
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... Set the EECON1 register for the write operation: • set EEPGD bit to point to program memory; • clear the CFGS bit to access program memory; • set WREN to enable byte writes. © 2007 Microchip Technology Inc. PIC18F1230/1330 The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long write cycle ...
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... TBLWT holding register. ; loop until buffers are full Advance Information © 2007 Microchip Technology Inc. ...
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... OSCFIF — PIE2 OSCFIE — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. © 2007 Microchip Technology Inc. PIC18F1230/1330 ; point to Flash program memory ; access Flash program memory ; enable write to memory ; disable interrupts ; write 55h ; write 0AAh ...
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... PIC18F1230/1330 NOTES: DS39758C-page 74 Advance Information © 2007 Microchip Technology Inc. ...
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... EECON2 is not a physical register. Reading EECON2 will read all ‘0’s. The EECON2 register is used exclusively in the memory write and erase sequences. © 2007 Microchip Technology Inc. PIC18F1230/1330 Control bit, EEPGD, determines if the access will be to program or data EEPROM memory. When clear, operations will access the data EEPROM memory ...
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... When a WRERR occurs, the EEPGD or FREE bit is not cleared. This allows tracing of the error condition. DS39758C-page 76 R/W-0 R/W-x R/W-0 (1) FREE WRERR WREN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Advance Information R/S-0 R/S bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... BSF INTCON, GIE SLEEP BCF EECON1, WREN © 2007 Microchip Technology Inc. PIC18F1230/1330 After a write sequence has been initiated, EECON1, EEADR and EEDATA cannot be modified. The WR bit will be inhibited from being set unless the WREN bit is set. The WREN bit must be set on a previous instruc- tion ...
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... Bit 2 TMR0IE INT0IE RBIE TMR0IF — FREE WRERR WREN — EEIP — LVDIP — EEIF — LVDIF — EEIE — LVDIE Advance Information Reset Bit 1 Bit 0 Values on Page: INT0IF RBIF — — 43 — — 43 — — 43 © 2007 Microchip Technology Inc. ...
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... Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply © 2007 Microchip Technology Inc. PIC18F1230/1330 EXAMPLE 8-1: MOVF ARG1, W MULWF ARG2 EXAMPLE 8-2: MOVF ARG1, W MULWF ARG2 ...
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... SUBWFB RES3 ; CONT_CODE : Advance Information SIGNED MULTIPLICATION ALGORITHM SIGNED MULTIPLY ROUTINE ; ARG1L * ARG2L -> ; PRODH:PRODL ; ARG1H * ARG2H -> ; PRODH:PRODL ; ARG1L * ARG2H -> ; PRODH:PRODL ; ; Add cross ; products ; ; ; ; ; ARG1H * ARG2L -> ; PRODH:PRODL ; ; Add cross ; products ; ; ; ; ARG2H:ARG2L neg? ; no, check ARG1 ; ; ; ; ARG1H:ARG1L neg? ; no, done ; ; ; © 2007 Microchip Technology Inc. ...
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... Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). © 2007 Microchip Technology Inc. PIC18F1230/1330 Reading the PORTA register reads the status of the pins, whereas writing to it, will write to the port latch. ...
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... LATA<7> data output. Disabled in external oscillator modes. I TTL PORTA<7> data input. Disabled in external oscillator modes. I ANA Oscillator crystal input or external clock source input. I ANA External clock source input. I ANA Timer1 oscillator input Fault detect input for PWM. Advance Information Description © 2007 Microchip Technology Inc. ...
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... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. Note 1: RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as ‘0’. © 2007 Microchip Technology Inc. PIC18F1230/1330 Bit 5 Bit 4 ...
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... The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTA and PORTB are used for the interrupt- on-change feature. Polling of PORTA and PORTB is not recommended while using the interrupt-on-change feature. PORTB is Advance Information and © 2007 Microchip Technology Inc. ...
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... Configuration on POR is determined by the PBADEN Configuration bit. Pins are configured as analog inputs by default when PBADEN is set and digital inputs when PBADEN is cleared. 2: Placement of T1OSI and T1OSO/T1CKI depends on the value of Configuration bit, T1OSCMX, of CONFIG3H. © 2007 Microchip Technology Inc. PIC18F1230/1330 I/O I/O ...
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... Bit 5 Bit 4 Bit 3 Bit 2 RB5 RB4 RB3 RB2 INT0IE RBIE TMR0IF INT3IE INT2IE INT1IE INT3IF C0OUT — — CMEN2 Advance Information Reset Bit 1 Bit 0 Values on Page: RB1 RB0 INT0IF RBIF 41 INT3IP RBIP 41 INT2IF INT1IF 41 CMEN1 CMEN0 42 © 2007 Microchip Technology Inc. ...
Page 89
... Individual interrupts can be disabled through their corresponding enable bits. © 2007 Microchip Technology Inc. PIC18F1230/1330 When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are compatible ...
Page 90
... INT2IP IPEN IPEN PEIE/GIEL IPEN TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP Advance Information Wake- Idle or Sleep modes Interrupt to CPU Vector to Location 0008h GIE/GIEH Interrupt to CPU Vector to Location 0018h GIE/GIEH PEIE/GIEL © 2007 Microchip Technology Inc. ...
Page 91
... None of the RB7:RB4 pins have changed state Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. © 2007 Microchip Technology Inc. PIC18F1230/1330 Note: Interrupt flag bits are set when an interrupt ...
Page 92
... This feature allows for software polling. DS39758C-page 90 R/W-1 R/W-1 R/W-1 INTEDG2 INTEDG3 TMR0IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Advance Information R/W-1 R/W-1 INT3IP RBIP bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 93
... Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2007 Microchip Technology Inc. PIC18F1230/1330 R/W-0 ...
Page 94
... R-0 R/W-0 R/W-0 TXIF CMP2IF CMP1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Advance Information Interrupt Enable bit, GIE software should ensure the R/W-0 R/W-0 CMP0IF TMR1IF bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 95
... PWM time base matched the value in PTPER register. Interrupt is issued according to the postscaler settings. PTIF must be cleared in software PWM time base has not matched the value in PTPER register bit 3-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. PIC18F1230/1330 R/W-0 U-0 R/W-0 EEIF — ...
Page 96
... TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt DS39758C-page 94 R-0 R/W-0 R/W-0 TXIE CMP2IE CMP1IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Advance Information R/W-0 R/W-0 CMP0IE TMR1IE bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 97
... Unimplemented: Read as ‘0’ bit 4 PTIE: PWM Time Base Interrupt Enable bit 1 = PWM enabled 0 = PWM disabled bit 3-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. PIC18F1230/1330 R/W-0 U-0 R/W-0 EEIE — LVDIE U = Unimplemented bit, read as ‘0’ ...
Page 98
... TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority DS39758C-page 96 R/W-1 R/W-1 R/W-1 TXIP CMP2IP CMP1IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Advance Information R/W-1 R/W-1 CMP0IP TMR1IP bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 99
... Unimplemented: Read as ‘0’ bit 4 PTIP: PWM Time Base Interrupt Priority bit 1 = High priority 0 = Low priority bit 3-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. PIC18F1230/1330 R/W-1 U-0 R/W-1 EEIP — LVDIP U = Unimplemented bit, read as ‘0’ ...
Page 100
... The operation of the SBOREN bit and the Reset flag bits is discussed in more detail in Section 4.1 “RCON Register”. R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) Advance Information (2) R/W-0 R/W-0 POR BOR bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 101
... MOVFF BSR_TEMP, BSR MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS © 2007 Microchip Technology Inc. PIC18F1230/1330 10.7 TMR0 Interrupt In 8-bit mode (which is the default), an overflow in the TMR0 register (FFh → 00h) will set flag bit, TMR0IF. In 16-bit mode, an overflow in the TMR0H:TMR0L register pair (FFFFh → 0000h) will set TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE (INTCON< ...
Page 102
... PIC18F1230/1330 NOTES: DS39758C-page 100 Advance Information © 2007 Microchip Technology Inc. ...
Page 103
... Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value © 2007 Microchip Technology Inc. PIC18F1230/1330 Figure 11-1 shows a simplified block diagram of the Timer0 module in 8-bit mode and Figure 11-2 shows a simplified block diagram of the Timer0 module in 16-bit mode. ...
Page 104
... T0PS2, T0PS1, T0PS0 1 Sync with Internal TMR0L Clocks Delay PSA Advance Information Data Bus 8 TMR0 Set Interrupt Flag bit TMR0IF on Overflow Set Interrupt TMR0 Flag bit TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 Data Bus<7:0> © 2007 Microchip Technology Inc. ...
Page 105
... RA7 RA6 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by Timer0. Note 1: RA6 and RA7 are enabled as I/O pins depending on the oscillator mode selected in CONFIG1H. © 2007 Microchip Technology Inc. PIC18F1230/1330 11.2.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control (i.e., it can be changed “ ...
Page 106
... PIC18F1230/1330 NOTES: DS39758C-page 104 Advance Information © 2007 Microchip Technology Inc. ...
Page 107
... TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Note 1: Placement of T1OSI and T1OSO/T1CKI depends on the value of the Configuration bit, T1OSCMX, of CONFIG3H. © 2007 Microchip Technology Inc. PIC18F1230/1330 Register 12-1 details the Timer1 Control register. This register controls the operating mode of the Timer1 module and contains the Timer1 Oscillator Enable bit (T1OSCEN) ...
Page 108
... OSC (1) Oscillator Internal 0 Clock T1CKPS1:T1CKPS0 TMR1CS 8 TMR1L TMR1ON On/Off 1 T1OSCEN F /4 OSC Enable 0 Internal (1) Oscillator Clock TMR1CS T1CKPS1:T1CKPS0 Advance Information Synchronized 0 Clock Input 1 Synchronize det 2 Peripheral Clocks Synchronized 0 Clock Input 1 T1SYNC Synchronize Prescaler det 2 Peripheral Clocks © 2007 Microchip Technology Inc. ...
Page 109
... Capacitor values are for design guidance only. © 2007 Microchip Technology Inc. PIC18F1230/1330 12.2.1 USING TIMER1 AS A CLOCK SOURCE The Timer1 oscillator is also available as a clock source in power-managed modes. By setting the System Clock Select bits, SCS1:SCS0 (OSCCON< ...
Page 110
... For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> = 1), as shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times. Advance Information © 2007 Microchip Technology Inc. ...
Page 111
... Timer1 Register High Byte T1CON RD16 T1RUN Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. © 2007 Microchip Technology Inc. PIC18F1230/1330 ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ; Asynchronous operation, external oscillator ...
Page 112
... PIC18F1230/1330 NOTES: DS39758C-page 110 Advance Information © 2007 Microchip Technology Inc. ...
Page 113
... Switched Reluctance Motors • Brushless DC (BLDC) Motors • Uninterruptible Power Supplies (UPS) • Multiple DC Brush Motors © 2007 Microchip Technology Inc. PIC18F1230/1330 The PWM module has the following features: • six PWM I/O pins with three duty cycle generators. Pins can be paired to acquire a complete half-bridge control ...
Page 114
... Override Logic PWM Channel 1 Generator 1 Dead-Time Generator and Override Logic PWM Channel 0 Generator 0 Dead-Time Generator and Override Logic Special Event Postscaler PTDIR Advance Information PWM5 (1) PWM4 PWM3 Output PWM2 Driver Block PWM1 PWM0 FLTA Special Event Trigger © 2007 Microchip Technology Inc. ...
Page 115
... In Complementary modes, the even PWM pins must always be the complement of the corresponding odd PWM pins. For example, PWM0 will be the complement of PWM1 and PWM2 will be the complement of PWM3. The dead-time generator © 2007 Microchip Technology Inc. PIC18F1230/1330 V DD Dead-Band ...
Page 116
... The PWM time base is configured through the PTCON0 and PTCON1 registers. The time base is enabled or disabled by respectively setting or clearing the PTEN bit in the PTCON1 register. Note: The PTMR register pair (PTMRL:PTMRH) is not cleared when the PTEN bit is cleared in software. Advance Information © 2007 Microchip Technology Inc. ...
Page 117
... The PWM time base can be configured for four different modes of operation: • Free-Running mode • Single-Shot mode • Continuous Up/Down Count mode • Continuous Up/Down Count mode with interrupts for double updates © 2007 Microchip Technology Inc. PIC18F1230/1330 PTMR Clock Timer Reset Up/Down Zero Match Timer ...
Page 118
... OSC /256 (1:64 prescale) OSC U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Advance Information R/W-0 R/W-0 PTMOD1 PTMOD0 bit Bit is unknown U-0 U-0 — — bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 119
... PWM I/O pin pair (PWM2, PWM3 the Complementary mode For PMOD2 PWM I/O pin pair (PWM4, PWM5 the Independent mode 0 = PWM I/O pin pair (PWM4, PWM5 the Complementary mode Note 1: Reset condition of PWMEN bits depends on the PWMPIN Configuration bit of CONFIG3L. © 2007 Microchip Technology Inc. PIC18F1230/1330 (1) (1) R/W-1 U-0 ...
Page 120
... Output overrides via the OVDCON register are synchronized to the PWM time base 0 = Output overrides via the OVDCON register are asynchronous DS39758C-page 118 R/W-0 R/W-0 U-0 SEVOPS0 SEVTDIR — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Advance Information R/W-0 R/W-0 UDIS OSYNC bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 121
... Write to the PTCON (PTCON0 or PTCON1) register • Any device Reset Note: The PTMR register is not cleared when PTCONx is written. © 2007 Microchip Technology Inc. PIC18F1230/1330 Table 13-1 shows the minimum PWM frequencies that can be generated with the PWM time base and the prescaler. ...
Page 122
... PWM time base begins to count upwards. The postscaler selection bits may be used in this Timer mode to reduce the frequency of the interrupt events. Figure 13-7 shows the interrupts in Continuous Up/ Down Count mode. Advance Information 001h 002h 001h 002h Up/Down Count mode © 2007 Microchip Technology Inc. ...
Page 123
... PWM TIME BASE INTERRUPTS, CONTINUOUS UP/DOWN COUNT MODE PRESCALER = 1 OSC PTMR 002h PTDIR bit PTMR_INT_REQ 1 1 PTIF bit PRESCALER = 1 PTMR 002h PTDIR bit 1 1 PTMR_INT_REQ PTIF bit Note 1: Interrupt flag bit, PTIF, is sampled here (every Q1). © 2007 Microchip Technology Inc. PIC18F1230/1330 FFFh 000h FFFh 000h ...
Page 124
... PTEN is active. It will yield unexpected results. To change the PWM Timer mode of operation, first clear the PTEN bit, load PTMOD bits with required data and then set PTEN 3FEh 3FFh 001h 000h 1 1 Advance Information 3FEh 3FDh 001h 002h © 2007 Microchip Technology Inc. ...
Page 125
... The PWM frequency is the inverse of period; or EQUATION 13-3: PWM FREQUENCY 1 PWM Frequency = PWM Period © 2007 Microchip Technology Inc. PIC18F1230/1330 The maximum resolution (in bits) for a given device oscillator and PWM frequency can be determined from the following formula: EQUATION 13-4: Resolution = The PWM resolutions and frequencies are shown for a selection of execution speeds and PTPER values in Table 13-2 ...
Page 126
... New PTPER Value = 007 Old PTPER Value = 004 1 0 DS39758C-page 124 Period Value Loaded from PTPER Buffer Register New Value Written to PTPER Buffer Period Value Loaded from PTPER Buffer Register New Value Written to PTPER Buffer Advance Information © 2007 Microchip Technology Inc. ...
Page 127
... duty cycle match occurs duty cycle match occurs duty cycle match occurs on Q4 © 2007 Microchip Technology Inc. PIC18F1230/1330 PTMR and the lower 2 bits are equal to Q1, Q2 Q4, depending on the lower two bits of the PDCx (when the prescaler is 1:1 or PTCKPS<1:0> = 00) ...
Page 128
... FIGURE 13-12: PTPER PTMR PDCx (old) Value PDCx (new) 0 Duty Cycle Active at Period Beginning of Period Duty Cycle Value Loaded from Buffer Register New Value Written to Duty Cycle Buffer Advance Information EDGE-ALIGNED PWM New Duty Cycle Latched © 2007 Microchip Technology Inc. ...
Page 129
... Duty Cycle Start of First PWM Period © 2007 Microchip Technology Inc. PIC18F1230/1330 Duty Cycle Value Loaded from Buffer Register New Values Written to Duty Cycle Buffer inactive for the entire PWM period. In addition, the output on the PWM pin will be active for the entire PWM period if the value in the Duty Cycle register is equal to or greater than the value in the PTPER register ...
Page 130
... I/O pin pair by clearing the appropriate PMODx bit in the PWMCON0 register. The PWM I/O pins are set to Complementary mode by default upon all kinds of device Resets. are the Advance Information TYPICAL LOAD FOR COMPLEMENTARY PWM OUTPUTS 3-Phase Load © 2007 Microchip Technology Inc. ...
Page 131
... DEAD-TIME INSERTION FOR COMPLEMENTARY PWM PDC1 Compare Output PWM1 PWM0 © 2007 Microchip Technology Inc. PIC18F1230/1330 13.7.1 DEAD-TIME INSERTION Each complementary output pair for the PWM module has a 6-bit down counter used to produce the dead- time insertion. As shown in Figure 13-17, each dead- time unit has a rising and falling edge detector connected to the duty cycle comparison output ...
Page 132
... Q clock corresponding to the Q clocks on which the PWM duty cycle match occurs. Advance Information R/W-0 R/W-0 DT1 DT0 bit Bit is unknown /4, OSC /16 /16, F /64, F /256 OSC OSC OSC /4) OSC /4, OSC /16) and the PWM time base pres- © 2007 Microchip Technology Inc. ...
Page 133
... OSC 4 μ /16 OSC © 2007 Microchip Technology Inc. PIC18F1230/1330 13.7.4 DEAD-TIME DISTORTION Note 1: For small PWM duty cycles, the ratio of dead time to the active PWM time may become large. In this case, the inserted dead time will introduce distortion into waveforms produced by the PWM mod- ule ...
Page 134
... The even channel is always the complement of the odd channel, with dead-time inserted, before the odd channel can be driven to its active state as shown in Figure 13-20. 2: Dead time inserted in the PWM channels even when they are in Override mode. Advance Information © 2007 Microchip Technology Inc. ...
Page 135
... Odd override bit is activated which causes the even PWM to deactivate. 3. Dead-time insertion. 4. Odd PWM activated after the dead time. 5. Odd override bit is deactivated which causes the odd PWM to deactivate. 6. Dead-time insertion. 7. Even PWM is activated after the dead time. © 2007 Microchip Technology Inc. PIC18F1230/1330 Advance Information DS39758C-page 133 ...
Page 136
... Bit is cleared R/W-0 R/W-0 R/W-0 POUT4 POUT3 POUT2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Advance Information control the commutation R/W-1 R/W-1 POVD1 POVD0 bit Bit is unknown R/W-0 R/W-0 POUT1 POUT0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 137
... PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 © 2007 Microchip Technology Inc. PIC18F1230/1330 13.11 PWM Output and Polarity Control There are three device Configuration bits associated with the PWM module that provide PWM output pin 5 6 control defined in the CONFIG3L register. They are: • ...
Page 138
... FAULT PIN ENABLE BIT By setting the bit FLTAEN in the FLTCONFIG register, the corresponding Fault input is enabled. If FLTAEN bit is cleared, then the Fault input has no effect on the PWM module. Advance Information I/O pin TTL or Schmitt Trigger © 2007 Microchip Technology Inc. ...
Page 139
... Inactive mode: Pins are deactivated (catastrophic failure) until FLTA is deasserted and FLTAS is cleared by the user only bit 0 FLTAEN: Fault A Enable bit 1 = Enable Fault Disable Fault A © 2007 Microchip Technology Inc. PIC18F1230/1330 13.12.3 PWM OUTPUTS WHILE IN FAULT CONDITION While in the Fault state (i.e., FLTA input is active), the PWM output signals are driven into their inactive states ...
Page 140
... The PWM Special Event Trigger has a postscaler that allows a 1:1 to 1:16 postscale ratio. The postscaler configured by writing the SEVOPS3:SEVOPS0 control bits in the PWMCON1 register. The Special Event Trigger output postscaler is cleared on any write to the SEVTCMP register pair any device Reset. Advance Information © 2007 Microchip Technology Inc. ...
Page 141
... Shaded cells are not used with the Power Control PWM. Note 1: Double-buffered register pairs. Refer to text for explanation of how these registers are read and written to. 2: Reset condition of PWMEN bits depends on the PWMPIN Configuration bit. © 2007 Microchip Technology Inc. PIC18F1230/1330 Bit 5 Bit 4 Bit 3 ...
Page 142
... PIC18F1230/1330 NOTES: DS39758C-page 140 Advance Information © 2007 Microchip Technology Inc. ...
Page 143
... Break Character Transmission • Synchronous – Master (half-duplex) with Selectable Clock Polarity • Synchronous – Slave (half-duplex) with Selectable Clock Polarity © 2007 Microchip Technology Inc. PIC18F1230/1330 The pins of the Enhanced USART are multiplexed with PORTA. In order to configure RA2/TX/CK and RA3/RX/ EUSART: • ...
Page 144
... Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Sync mode. DS39758C-page 142 R/W-0 R/W-0 R/W-0 (1) SYNC SENDB BRGH U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Advance Information R-1 R/W-0 TRMT TX9D bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 145
... OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN overrun error bit 0 RX9D: 9th bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. © 2007 Microchip Technology Inc. PIC18F1230/1330 R/W-0 R/W-0 R-0 CREN ...
Page 146
... Baud rate measurement disabled or completed Synchronous mode: Unused in this mode. DS39758C-page 144 R/W-0 R/W-0 U-0 SCKP BRG16 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Advance Information R/W-0 R/W-0 WUE ABDEN bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 147
... Legend Don’t care value of SPBRGH:SPBRG register pair © 2007 Microchip Technology Inc. PIC18F1230/1330 to use the high baud rate (BRGH = 1), or the 16-bit BRG to reduce the baud rate error, or achieve a slow baud rate for a fast oscillator frequency. Writing a new value to the SPBRGH:SPBRG registers causes the BRG timer to be reset (or cleared) ...
Page 148
... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG. DS39758C-page 146 Bit 5 Bit 4 Bit 3 Bit 2 TXEN SYNC SENDB BRGH SREN CREN ADDEN FERR — SCKP BRG16 — Advance Information Reset Values Bit 1 Bit 0 on Page: TRMT TX9D 42 OERR RX9D 42 WUE ABDEN © 2007 Microchip Technology Inc. ...
Page 149
... Microchip Technology Inc. PIC18F1230/1330 SYNC = 0, BRGH = 0, BRG16 = 20.000 MHz F = 10.000 MHz OSC OSC SPBRG Actual % Rate value Rate Error Error (K) (decimal) (K) — ...
Page 150
... Error (decimal) (K) (decimal) 8332 0.300 -0.01 6665 2082 1.200 -0.04 1665 1040 2.400 -0.04 832 259 9.615 -0.16 207 129 19.230 -0.16 103 42 57.142 0. 117.647 -2.12 16 SPBRG % value (decimal) 832 207 103 25 12 — — © 2007 Microchip Technology Inc. ...
Page 151
... RX is detected. The value in the RCREG needs to be read to clear the RCIF interrupt. The contents of RCREG should be discarded. © 2007 Microchip Technology Inc. PIC18F1230/1330 Note 1: If the WUE bit is set with the ABDEN bit, Auto-Baud Rate Detection will occur on the byte following the Break character ...
Page 152
... ABDOVF bit BRG Value XXXXh DS39758C-page 150 Edge #2 Edge #3 Edge #1 bit 1 bit 3 Start bit 2 bit 0 bit 4 XXXXh XXXXh Start bit 0 0000h Advance Information 001Ch Edge #4 Edge #5 bit 5 bit 7 bit 6 Stop bit Auto-Cleared 1Ch 00h FFFFh 0000h © 2007 Microchip Technology Inc. ...
Page 153
... TXEN BRG16 SPBRGH SPBRG Baud Rate Generator © 2007 Microchip Technology Inc. PIC18F1230/1330 Once the TXREG register transfers the data to the TSR register (occurs in one T and the TXIF flag bit (PIR1<4>) is set. This interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TXIE (PIE1< ...
Page 154
... Advance Information bit 7/8 Stop bit Start bit bit 0 Stop bit Word 2 Word 2 Transmit Shift Reg. Reset Bit 1 Bit 0 Values on Page: INT0IF RBIF 41 CMP0IF TMR1IF 43 CMP0IE TMR1IE 43 CMP0IP TMR1IP 43 OERR RX9D 42 42 TRMT TX9D 42 WUE ABDEN © 2007 Microchip Technology Inc. ...
Page 155
... Baud Rate CLK BRG16 SPBRGH SPBRG Baud Rate Generator Pin Buffer and Control RX SPEN © 2007 Microchip Technology Inc. PIC18F1230/1330 14.2.3 SETTING UP 9-BIT MODE WITH ADDRESS DETECT This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with Address Detect Enable: 1. ...
Page 156
... Sync Break event is over. Advance Information Start Stop Stop bit bit 7/8 bit bit Reset Bit 1 Bit 0 Values on Page: INT0IF RBIF 41 CMP0IF TMR1IF 43 CMP0IE TMR1IE 43 CMP0IP TMR1IP 43 OERR RX9D 42 42 TRMT TX9D 42 WUE ABDEN The interrupt is generated © 2007 Microchip Technology Inc. ...
Page 157
... If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur before the oscillator is ready. This sequence should not depend on the presence of Q clocks. 2: The EUSART remains in Idle while the WUE bit is set. © 2007 Microchip Technology Inc. PIC18F1230/1330 14.2.4.2 Special Considerations Using ...
Page 158
... Note that following a Break character, the user will typically want to enable the Auto-Baud Rate Detect feature. For both methods, the user can set the ABDEN bit once the TXIF interrupt is observed. bit 0 bit 1 bit 11 Break Advance Information Stop bit Auto-Cleared © 2007 Microchip Technology Inc. ...
Page 159
... Flag) TRMT bit TXEN bit ‘1’ Note: Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words. © 2007 Microchip Technology Inc. PIC18F1230/1330 Once the TXREG register transfers the data to the TSR register (occurs in one T the TXIF flag bit (PIR1<4>) is set. The interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TXIE (PIE1< ...
Page 160
... SREN CREN ADDEN FERR TXEN SYNC SENDB BRGH — SCKP BRG16 — Advance Information bit 7 bit 6 Reset Bit 1 Bit 0 Values on Page: INT0IF RBIF 41 CMP0IF TMR1IF 43 CMP0IE TMR1IE 43 CMP0IP TMR1IP 43 OERR RX9D 42 42 TRMT TX9D 42 WUE ABDEN © 2007 Microchip Technology Inc. ...
Page 161
... EUSART Baud Rate Generator Register High Byte SPBRG EUSART Baud Rate Generator Register Low Byte Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception. © 2007 Microchip Technology Inc. PIC18F1230/1330 3. Ensure bits, CREN and SREN, are clear. ...
Page 162
... CMP2IP CMP1IP SREN CREN ADDEN FERR TXEN SYNC SENDB BRGH — SCKP BRG16 — Advance Information Reset Bit 1 Bit 0 Values on Page: INT0IF RBIF 41 CMP0IF TMR1IF 43 CMP0IE TMR1IE 43 CMP0IP TMR1IP 43 OERR RX9D 42 42 TRMT TX9D 42 WUE ABDEN © 2007 Microchip Technology Inc. ...
Page 163
... EUSART Baud Rate Generator Register High Byte SPBRG EUSART Baud Rate Generator Register Low Byte Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception. © 2007 Microchip Technology Inc. PIC18F1230/1330 To set up a Synchronous Slave Reception: 1. ...
Page 164
... PIC18F1230/1330 NOTES: DS39758C-page 162 Advance Information © 2007 Microchip Technology Inc. ...
Page 165
... A/D Idle bit 0 ADON: A/D On bit 1 = A/D Converter module is enabled 0 = A/D Converter module is disabled © 2007 Microchip Technology Inc. PIC18F1230/1330 The ADCON0 register, shown in Register 15-1, controls the operation of the A/D module. The ADCON1 register, shown in Register 15-2, configures the functions of the port pins. The ADCON2 register, shown in Register 15-3, configures the A/D clock source, programmed acquisition time and justification ...
Page 166
... This bit is unused and reads as ‘0’ if pin is not configured for use as RA6 DS39758C-page 164 (1,2) R/W-0 R/W-0 R/W VCFG0 PCFG3 PCFG2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared + source) REF + REF DD (1,2) (1) (1) (1) Advance Information (1) (1) (1) R/W R/W PCFG1 PCFG0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 167
... F /2 OSC Note 1: If the A/D F clock source is selected, a delay of one T RC clock starts. This allows the SLEEP instruction to be executed before starting a conversion. © 2007 Microchip Technology Inc. PIC18F1230/1330 R/W-0 R/W-0 R/W-0 ACQT1 ACQT0 ADCS2 U = Unimplemented bit, read as ‘0’ ...
Page 168
... A/D Interrupt Flag bit, ADIF, is set. The block diagram of the A/D module is shown in Figure 15-1. V AIN (Input Voltage) VCFG0 REF Advance Information the result is loaded into CHS1:CHS0 0011 AN3 0010 AN2 0001 AN1 0000 AN0 © 2007 Microchip Technology Inc. the ...
Page 169
... SS = Sampling Switch C = Sample/Hold Capacitance (from DAC) HOLD R = Sampling Switch Resistance SS © 2007 Microchip Technology Inc. PIC18F1230/1330 5. Wait for A/D conversion to complete, by either: • Polling for the GO/DONE bit to be cleared OR • Waiting for the A/D interrupt 6. Read A/D Result registers (ADRESH:ADRESL); ...
Page 170
... C HOLD . The sampling Rs Conversion Error V DD Temperature (- HOLD ln(1/2048) S COFF ) ln(1/2047) S Advance Information the minimum acquisition time, . This calculation is ACQ the following application system = 2.5 kΩ ≤ 1/2 LSb 5V → kΩ 85°C (system max ms. © 2007 Microchip Technology Inc. ...
Page 171
... For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or the A/D accuracy may be out of specification. 4: Low-power (PIC18LF1230/1330) devices only. © 2007 Microchip Technology Inc. PIC18F1230/1330 15.4 Selecting the A/D Conversion Clock The A/D conversion time per bit is defined as T ...
Page 172
... Analog levels on a digitally configured converted. 2: Analog levels on any pin defined as a digital input may cause the digital input clock to buffer to consume current out of the RC device’s specification limits. Advance Information OH input will be accurately © 2007 Microchip Technology Inc. ...
Page 173
... Conversion starts Time (Holding capacitor is disconnected) Set GO/DONE bit (Holding capacitor continues acquiring input) © 2007 Microchip Technology Inc. PIC18F1230/1330 After the A/D conversion is completed or aborted wait is required before the next acquisition can AD be started. After this wait, acquisition on the selected channel is automatically started ...
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... VCFG0 PCFG3 PCFG2 ACQT2 ACQT1 ACQT0 ADCS2 (2) RA5 RA4 RA3 RA2 Advance Information Reset Bit 1 Bit 0 Values on Page: INT0IF RBIF 41 CMP0IF TMR1IF 43 CMP0IE TMR1IE 43 CMP0IP TMR1IP GO/DONE ADON 42 PCFG1 PCFG0 42 ADCS1 ADCS0 42 RA1 RA0 44 43 © 2007 Microchip Technology Inc. ...
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... Comparator 1 is disabled bit 0 CMEN0: Comparator 0 Enable bit 1 = Comparator 0 is enabled 0 = Comparator 0 is disabled © 2007 Microchip Technology Inc. PIC18F1230/1330 Section 17.0 Module”). The digital outputs are not available at the pin level and can only be read through the control register, CMCON (Register 16-1). CMCON also selects the comparator input ...
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... Any read or write of CMCON will end the mismatch condition. b) Clear flag bit CMPxIF. A mismatch condition will continue to set flag bit CMPxIF. Reading CMCON will end the mismatch condition and allow flag bit CMPxIF to be cleared. the Advance Information © 2007 Microchip Technology Inc. ...
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... LEAKAGE © 2007 Microchip Technology Inc. PIC18F1230/1330 16.9 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 16-2. Since the analog pins are connected to a digital output, they have reverse biased diodes to V and V . The analog input, therefore, must be between ...
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... PORTA Data Latch Register (Read and Write to Data Latch) PORTA Data Direction Control Register RB5 RB4 RB3 RB2 Advance Information Reset Bit 1 Bit 0 Values on Page: CMEN1 CMEN0 42 CVR1 CVR0 42 INT0IF RBIF 41 CMP0IF TMR1IF 43 CMP0IE TMR1IE 43 CMP0IP TMR1IP 43 RA1 RA0 RB1 RB0 © 2007 Microchip Technology Inc. ...
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... REF When CVRR = 0: /4) + ((CVR3:CVR0)/32) • ( (CV REF RSRC © 2007 Microchip Technology Inc. PIC18F1230/1330 used is selected by the CVRR bit (CVRCON<5>). The primary difference between the ranges is the size of the steps selected (CVR3:CVR0), with one range offering finer resolution. The equations used to calculate the output of the ...
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... CVRR (CVRCON<5>). The CVR value select bits are also cleared. Bit 5 Bit 4 Bit 3 Bit 2 CVRR CVRSS CVR3 CVR2 C0OUT — — CMEN2 Advance Information CV REF Reset Bit 1 Bit 0 Values on Page: CVR1 CVR0 42 CMEN1 CMEN0 42 © 2007 Microchip Technology Inc. ...
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... Minimum setting Note 1: See Table 22-4 in Section 22.0 “Electrical Characteristics” for the specifications. © 2007 Microchip Technology Inc. PIC18F1230/1330 The Low-Voltage Detect Control register (Register 18-1) completely controls the operation of the LVD module. This allows the circuitry to be “turned off” by the user under software control, which minimizes the current consumption for the device ...
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... The comparator then generates an interrupt signal by setting the LVDIF bit. The trip point voltage is software programmable to any values. The trip point is selected by programming the LVDL3:LVDL0 bits (LVDCON<3:0>). DD LVDL3:LVDL0 LVDCON Register LVDEN Internal Voltage Reference Advance Information Set LVDIF © 2007 Microchip Technology Inc. ...
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... DD LVDIF Enable LVD IRVST Internal reference is stable © 2007 Microchip Technology Inc. PIC18F1230/1330 Depending on the application, the LVD module does not need to be operating constantly. To decrease the current requirements, the LVD circuitry may only need to be enabled for short periods where the voltage is checked ...
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... IRVST LVDEN LVDL3 LVDL2 INT0IE RBIE TMR0IF — EEIF — LVDIF — EEIE — LVDIE — EEIP — LVDIP Advance Information Reset Bit 1 Bit 0 Values on Page: LVDL1 LVDL0 42 INT0IF RBIF 41 — — 43 — — 43 — — 43 © 2007 Microchip Technology Inc. ...
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... Note 1: DEVID registers are read-only and cannot be programmed by the user. © 2007 Microchip Technology Inc. PIC18F1230/1330 The inclusion of an internal RC oscillator also provides the additional benefits of a Fail-Safe Clock Monitor (FSCM) and Two-Speed Start-up ...
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... External RC oscillator, CLKO function on RA6 0010 = HS oscillator 0001 = XT oscillator 0000 = LP oscillator DS39758C-page 184 U-0 R/P-0 R/P-1 — FOSC3 FOSC2 U = Unimplemented bit, read as ‘0’ Unchanged from programmed state Advance Information R/P-1 R/P-1 FOSC1 FOSC0 bit 0 © 2007 Microchip Technology Inc. ...
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... PWRTEN: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled Note 1: See Section 22.1 “DC Characteristics” for the specifications. 2: The Power-up Timer is decoupled from Brown-out Reset, allowing these features to be independently controlled. © 2007 Microchip Technology Inc. PIC18F1230/1330 R/P-1 R/P-1 R/P-1 (1) (1) BORV1 ...
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... WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on the SWDTEN bit) DS39758C-page 186 R/P-1 R/P-1 R/P-1 WDTPS3 WDTPS2 WDTPS1 U = Unimplemented bit, read as ‘0’ Unchanged from programmed state Advance Information R/P-1 R/P-1 WDTPS0 WDTEN bit 0 © 2007 Microchip Technology Inc. ...
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... Polarity control bits, HPOL and LPOL, define PWM signal output active and inactive states, PWM states generated by the Fault inputs or PWM manual override. 2: When PWMPIN = 0, PWMEN<2:0> = 100. PWM output polarity is defined by HPOL and LPOL. © 2007 Microchip Technology Inc. PIC18F1230/1330 U-0 R/P-1 ...
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... FLTAMX: FLTA MUX bit 1 = FLTA is muxed onto RA5 0 = FLTA is muxed onto RA7 DS39758C-page 188 U-0 R/P-0 U-0 — T1OSCMX — Unimplemented bit, read as ‘0’ Unchanged from programmed state Advance Information U-0 R/P-1 — FLTAMX bit 0 © 2007 Microchip Technology Inc. ...
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... Instruction set extension and Indexed Addressing mode enabled 0 = Instruction set extension and Indexed Addressing mode disabled bit 5-4 BBSIZ<1:0>: Boot Block Size Select bits For PIC18F1330 device Boot Block size Boot Block size 01 = 512W Boot Block size 00 = 256W Boot Block size ...
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... U = Unimplemented bit, read as ‘0’ Unchanged from programmed state U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ Unchanged from programmed state Advance Information R/C-1 R/C-1 CP1 CP0 bit 0 U-0 U-0 — — bit 0 © 2007 Microchip Technology Inc. ...
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... Configuration registers are not write-protected 0 = Configuration registers are write-protected bit 4-0 Unimplemented: Read as ‘0’ Note 1: This bit is read-only in normal execution mode; it can be written only in Program mode. © 2007 Microchip Technology Inc. PIC18F1230/1330 U-0 U-0 — — Unimplemented bit, read as ‘0’ ...
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... U = Unimplemented bit, read as ‘0’ Unchanged from programmed state U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ Unchanged from programmed state Advance Information R/C-1 R/C-1 EBTR1 EBTR0 bit 0 U-0 U-0 — — bit 0 © 2007 Microchip Technology Inc. ...
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... Legend Read-only bit P = Programmable bit -n = Value when device is unprogrammed bit 7-0 DEV10:DEV3: Device ID bits These bits are used with the DEV2:DEV0 bits in the DEVID1 register to identify part number. © 2007 Microchip Technology Inc. PIC18F1230/1330 REV4 REV3 REV2 U = Unimplemented bit, read as ‘0’ ...
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... WDT enable Configuration bit, but only if the Configuration bit has disabled the WDT. WDT Counter ÷128 Programmable Postscaler 1:1 to 1:32,768 4 Advance Information Wake-up from Power-Managed Modes WDT Reset Reset © 2007 Microchip Technology Inc. ...
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... The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”. 2: This bit has no effect if the Configuration bit, WDTEN, is enabled. © 2007 Microchip Technology Inc. PIC18F1230/1330 U-0 U-0 — ...
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... Reset or Sleep mode (1) (1) OST T PLL 1 2 n-1 n Clock (2) Transition OSTS bit Set = 2 ms (approx). These intervals are not shown to scale. PLL . OSC Advance Information instructions (refer SLEEP © 2007 Microchip Technology Inc. to ...
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... See Section 3.1.4 “Multiple Sleep Commands” and Section 19.3.1 “Special Considerations for Using Two-Speed Start-up” for more details. © 2007 Microchip Technology Inc. PIC18F1230/1330 To use a higher clock speed on wake-up, the INTOSC or postscaler clock sources can be selected to provide a higher clock speed by setting bits, IRCF2:IRCF0, immediately after Reset ...
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... Using Two-Speed Start-up” also possible to select another clock configuration and enter an alternate power-managed mode while waiting for the primary clock to become stable. When the new power- managed mode is selected, the primary clock is disabled. Advance Information Failure Detected CM Test © 2007 Microchip Technology Inc. ...