PIC18F1330-I/SO Microchip Technology, PIC18F1330-I/SO Datasheet
PIC18F1330-I/SO
Specifications of PIC18F1330-I/SO
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PIC18F1330-I/SO Summary of contents
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... DEVICE OVERVIEW This document includes the programming specifications for the following devices: • PIC18F1230 • PIC18F1330 • PIC18F1330-ICD 2.0 PROGRAMMING OVERVIEW PIC18F1230/1330 devices can be programmed using the high-voltage In-Circuit Serial Programming™ (ICSP™) method. This method can be done with the device in the user’ ...
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... RB2/INT2/KBI2/CMP2/T1OSO 3 16 RA7/OSC1/CLKI/T1OSI 4 15 RA6/OSC2/CLKO/T1OSO RB7/PWM5/PGD 7 12 RB6/PWM4/PGC 8 11 RB5/PWM3 9 10 RB4/PWM2 1 20 RB3/INT3/KBI3/CMP1/T1OSI 2 19 RB2/INT2/KBI2/CMP2/T1OSO + 3 18 RA7/OSC1/CLKI/T1OSI 4 17 RA6/OSC2/CLKO/T1OSO RB7/PWM5/PGD RB6/PWM4/PGC RB5/PWM3 10 11 RB4/PWM2 (1) (1) (1) (2) /FLTA (1) /AN3 /AV DD (1) (1) (1) (2) /FLTA (1) /AN3 DD DD © 2009 Microchip Technology Inc. ...
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... MCLR/V /RA5/FLTA RA2/TX/CK Note 1: Placement of T1OSI and T1OSO depends on the value of the Configuration bit, T1OSCMX of CONFIG3H. 2: Pin feature is dependent on device configuration. 3: Placement of FLTA depends on the value of the Configuration bit, FLTAMX of CONFIG3H. © 2009 Microchip Technology Inc. PIC18F1230/1330 21 RA7/OSC1/CLKI/T1OSI RA6/OSC2/CLKO/T1OSO PIC18F1X30 18 NC ...
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... PIC18F1230/1330 FIGURE 2-3: PIC18F1330-ICD DEVICE PIN DIAGRAM 28-Pin QFN (3) MCLR/V /RA5/FLTA PP (2) PP (2) ICRST /ICV RA2/TX/CK Note 1: Placement of T1OSI and T1OSO depends on the value of the Configuration bit, T1OSCMX of CONFIG3H. 2: Pin feature is dependent on device configuration. 3: Placement of FLTA depends on the value of the Configuration bit, FLTAMX of CONFIG3H. ...
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... Memory Maps For the PIC18F1330 device, the code memory space extends from 00000h to 01FFFh (8 Kbytes) in two 4-Kbyte blocks. For the PIC18F1230 device, the code memory space extends from 00000h to 00FFFh (4 Kbytes) in two 2-Kbyte blocks. Addresses 00000h through 07FFh, however, define a “Boot Block” region that is treated separately from Block 0 ...
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... PIC18F1230/1330 FIGURE 2-5: MEMORY MAP AND CODE MEMORY SPACE FOR THE PIC18F1330 DEVICE 000000h Code Memory Unimplemented Read as ‘0’ 01FFFFh 200000h Configuration and ID Space 3FFFFFh Note: Sizes of memory areas are not to scale. * Boot Block size is determined by the BBSIZ<1:0> bits in CONFIG4L. ...
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... Configuration and ID Space 2FFFFFh 3FFFFFh Note: Sizes of memory areas are not to scale. © 2009 Microchip Technology Inc. PIC18F1230/1330 2.3.1 MEMORY ADDRESS POINTER Memory in the address space, 0000000h to 3FFFFFh, is addressed via the Table Pointer register, which is comprised of three pointer registers: • TBLPTRU at RAM address 0FF8h • ...
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... Verify mode places all unused I/Os in the high-impedance state. FIGURE 2-8: ENTERING HIGH-VOLTAGE PROGRAM/VERIFY MODE P13 P12 P1 D110 MCLR RA5/FLTA V DD PGD PGC PGD = Input FIGURE 2-9: EXITING HIGH-VOLTAGE PROGRAM/VERIFY MODE P16 P17 MCLR RA5/FLTA D110 V DD PGD PGC PGD = Input © 2009 Microchip Technology Inc. /RA5/FLTA to ...
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... PGC PGD 4-Bit Command © 2009 Microchip Technology Inc. PIC18F1230/1330 TABLE 2-3: Core Instruction (shift in16-bit instruction) Shift out TABLAT Register Table Read Table Read, Post-Increment Table Read, Post-Decrement Table Read, Pre-Increment Table Write Table Write, Post-Increment by 2 Table Write, Start Programming, ...
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... PIC18F1230/1330 2.7 28-Pin PIC18F1330-ICD Device (Dedicated ICD Port) The PIC18F1330-ICD 28-pin QFN device has a dedicated ICSP/ICD port. The primary purpose of this port is to provide an alternate In-Circuit Debugging (ICD) option and free the pins (RB6, RB7 and MCLR) that would normally be used for debugging the applica- tion ...
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... P11). During this time, PGC may continue to toggle but PGD must be held low. © 2009 Microchip Technology Inc. PIC18F1230/1330 The code sequence to erase the entire device is shown in Table 3-2 and the flowchart is shown in Figure 3-1. ...
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... PIC18F1230/1330 device. The timing diagram that details the Start Programming command and parameters P9 and P10 is shown in Figure 3-5. Note: The TBLPTR register can point to any byte within the row intended for erase. P10 P11 Erase Time 16-Bit Data Payload © 2009 Microchip Technology Inc. ...
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... NOP – hold PGC high for time P9 and low for time P10. Step 4: Repeat step 3, with Address Pointer incremented by 64 until all rows are erased. FIGURE 3-3: SINGLE ROW ERASE CODE MEMORY FLOW Addr = Addr + 64 © 2009 Microchip Technology Inc. PIC18F1230/1330 Core Instruction EECON1, EEPGD EECON1, CFGS ...
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... Note: The TBLPTR register must point to the same region when initiating the program- ming sequence as it did when the write buffers were loaded. TABLE 3-4: Device PIC18F1230 PIC18F1330 Core Instruction BSF EECON1, EEPGD BCF EECON1, CFGS MOVLW <Addr[21:16]> MOVWF TBLPTRU MOVLW <Addr[15:8]> ...
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... TABLE WRITE AND START PROGRAMMING INSTRUCTION TIMING (1111 PGC P5 PGD 4-Bit Command 16-Bit Data Payload © 2009 Microchip Technology Inc. PIC18F1230/1330 Start LoopCount = 0 Configure Device for Writes Load 2 Bytes to Write Buffer at <Addr> All No bytes written? Yes Start Write Sequence and Hold PGC High until Done ...
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... MOVWF TBLPTRL Write 2 bytes and post-increment address by 2. Repeat as many times as necessary to fill the write buffer Write 2 bytes and start programming. NOP - hold PGC high for time P9 and low for time P10. BCF EECON1, WREN © 2009 Microchip Technology Inc. ...
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... PGC P5 PGD 4-Bit Command BSF EECON1 PGC Poll WR bit PGD 4-Bit Command © 2009 Microchip Technology Inc. PIC18F1230/1330 FIGURE 3-6: P5A P11A Poll WR bit, Repeat until Clear (see below) PGD = Input P5A 4-Bit Command MOVWF TABLAT MOVF EECON1 PGD = Input PROGRAM DATA FLOW ...
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... Core Instruction BCF EECON1, EEPGD BCF EECON1, CFGS MOVLW <Addr> MOVWF EEADR MOVLW <AddrH> MOVWF EEADRH MOVLW <Data> MOVWF EEDATA BSF EECON1, WREN BSF EECON1, WR MOVF EECON1 MOVWF TABLAT NOP (1) Shift out data BCF EECON1, WREN © 2009 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC18F1230/1330 Table 3-8 demonstrates the code sequence required to write the ID locations. In order to modify the ID locations, refer to the methodology described in Section 3.2.1 “Modifying Code Memory”. As with code memory, the ID locations must be erased before being modified ...
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... NOP - hold PGC high for time P9 and low for time P10. MOVLW 01h MOVWF TBLPTRL Load 2 bytes and start programming. NOP - hold PGC high for time P9 and low for time P10. Load Odd Configuration Address Program Delay P9 and P10 Time for Write Start MSB Done © 2009 Microchip Technology Inc. ...
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... PGD = Input © 2009 Microchip Technology Inc. PIC18F1230/1330 The 4-bit command is shifted in, LSb first. The read is executed during the next 8 clocks, then shifted out on PGD during the last 8 clocks, LSb to MSb. A delay of P6 must be introduced after the falling edge of the 8th PGC of the operand to allow PGD to transition from an input to an output ...
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... Pointer back to 00000h, rather than point to unimplemented address, 02000h. Set TBLPTR = 200000h Increment Pointer Failure, Report Error No Read Low Byte with Post-Increment Read High Byte with Post-Increment Does No Word = Expect Failure, Data? Report Error Yes All ID locations verified? Yes Done © 2009 Microchip Technology Inc. ...
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... Step 4: Load data into the Serial Data Holding register. 0000 50 A8 0000 6E F5 0000 00 00 0010 <MSB><LSB> Note 1: The <LSB> is undefined. The <MSB> is the data. © 2009 Microchip Technology Inc. PIC18F1230/1330 FIGURE 4-3: Core Instruction BCF EECON1, EEPGD BCF EECON1, CFGS MOVLW <Addr> MOVWF ...
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... Section 4.4 “Read Data EEPROM Memory” and Section 4.2 “Verify Code Memory and ID Locations” for implementation details. FIGURE 4-5: Start Blank Check Device device blank? Abort P5A 5 6 MSb Fetch Next 4-Bit Command PGD = Input BLANK CHECK FLOW Is Yes Continue No © 2009 Microchip Technology Inc. ...
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... Note 1: DEVID registers are read-only and cannot be programmed by the user. TABLE 5-2: DEVICE ID VALUE Device PIC18F1230 PIC18F1330 PIC18F1330-ICD Note: The ‘x’s in DEVID1 contain the device revision code. © 2009 Microchip Technology Inc. PIC18F1230/1330 5.2 Device ID Word The Device ID Word for the PIC18F1230/1330 devices is located at 3FFFFEh:3FFFFFh ...
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... Watchdog Timer Postscaler Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 © 2009 Microchip Technology Inc. ...
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... Extended Instruction Set Enable bit 1 = Instruction set extension and Indexed Addressing mode enabled 0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode) Boot Block Size Select bits For PIC18F1330 device Boot Block size Boot Block size 01 = 512W Boot Block size 00 = 256W Boot Block size ...
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... Boot Block is protected from table reads executed in other blocks Device ID bits These bits are used with the DEV<2:0> bits in the DEVID1 register to identify the part number. Device ID bits These bits are used with the DEV<10:3> bits in the DEVID2 register to identify the part number. © 2009 Microchip Technology Inc. ...
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... EEPROM information must be included. An option to not include the data EEPROM information may be provided. When embedding data EEPROM information in the hex file, it should start at address F00000h. Microchip Technology Inc. believes that this feature is important for the benefit of the end customer. © 2009 Microchip Technology Inc. PIC18F1230/1330 5 ...
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... Description CFGW = Configuration Word SUM[a:b] = Sum of locations inclusive SUM_ID = Byte-wise sum of lower four bits of all customer ID locations + = Addition & = Bit-wise AND DS39752B-page 30 Checksum © 2009 Microchip Technology Inc. 0xAA at 0 Blank and Max Value Address F33E F294 F521 F4C7 F732 F6D8 ...
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... PIC18F1330 Boot 1 kW SUM(0800:FFF)+SUM(1000:1FFF)+(CONFIG0 & 0000)+(CONFIG1 & 00CF)+ (CONFIG2 & 001F)+(CONFIG3 & 001F)+(CONFIG4 & 000E)+ (CONFIG5 & ...
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... V ; this can cause spurious program IL IHH (for LP, HS, HS/PLL and XT modes only) + OSC is the Power-up Timer period and T PWRT for the PIC18F1330-ICD device. PP Units Conditions V (Note 2) V (Note 2) V Externally timed, row erases and all writes V Self-timed, bulk erases only (Note 3) μ ...
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... DD 0 — and V IL IHH (for LP, HS, HS/PLL and XT modes only) + OSC is the Power-up Timer period and T PWRT for the PIC18F1330-ICD device. PP Units Conditions ms μs ns (Note 2) ns μs (Note this can cause spurious program is the oscillator period. For ...
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... PIC18F1230/1330 NOTES: DS39752B-page 34 © 2009 Microchip Technology Inc. ...
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... PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2009 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...