ATMEGA8535L-8MU Atmel, ATMEGA8535L-8MU Datasheet - Page 129

• Manufacturer Part Number: ATMEGA8535L-8MU
• Description: IC AVR MCU 8K 8MHZ 3V 44-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8535L-8MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-VQFN Exposed Pad
• Processor Series: ATMEGA8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI, TWI, UART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 44MLF EP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• For Use With: ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2502K–AVR–10/06
Table 51. Waveform Generation Mode Bit Description
Note:
• Bit 5:4 – COM21:0: Compare Match Output Mode
These bits control the Output Compare pin (OC2) behavior. If one or both of the
COM21:0 bits are set, the OC2 output overrides the normal port functionality of the I/O
pin it is connected to. However, note that the Data Direction Register (DDR) bit corre-
sponding to OC2 pin must be set in order to enable the output driver.
When OC2 is connected to the pin, the function of the COM21:0 bits depends on the
WGM21:0 bit setting. Table 52 shows the COM21:0 bit functionality when the WGM21:0
bits are set to a Normal or CTC mode (non-PWM).
Table 52. Compare Output Mode, non-PWM Mode
Table 53 shows the COM21:0 bit functionality when the WGM21:0 bits are set to fast
PWM mode.
Table 53. Compare Output Mode, Fast PWM Mode
Note:
Mode
COM21
0
1
2
3
COM21
0
0
1
1
0
0
1
1
1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 def-
1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the
WGM21
(CTC2)
COM20
initions. However, the functionality and location of these bits are compatible with
previous versions of the timer.
Compare Match is ignored, but the set or clear is done at TOP. See “Fast PWM
Mode” on page 123 for more details.
0
0
1
1
0
1
0
1
COM20
WGM20
(PWM2)
0
1
0
1
Description
Normal port operation, OC2 disconnected.
Reserved
Clear OC2 on Compare Match, set OC2 at TOP (Non-Inverting).
Set OC2 on Compare Match, clear OC2 at TOP (Inverting).
0
1
0
1
Description
Normal port operation, OC2 disconnected.
Toggle OC2 on Compare Match.
Clear OC2 on Compare Match.
Set OC2 on Compare Match.
Timer/Counter Mode
of Operation
Normal
PWM, Phase Correct
CTC
Fast PWM
(1)
(1)
TOP
0xFF
0xFF
OCR2
0xFF
ATmega8535(L)
Update of
OCR2
Immediate
TOP
Immediate
BOTTOM
TOV2 Flag
Set on
MAX
BOTTOM
MAX
MAX
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