ATMEGA8515-16PU Atmel, ATMEGA8515-16PU Datasheet - Page 33

• Manufacturer Part Number: ATMEGA8515-16PU
• Description: IC AVR MCU 8K 16MHZ 5V 40DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8515-16PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Cpu Speed: 16 MIPS
• Eeprom Memory: 512 Bytes
• Input Output: 35
• Interface: SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 8K Bytes
• Timers: 1-8-bit, 1-16-bit
• Voltage, Range: 4.5-5.5 V
• Processor Series: ATMEGA8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 2
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

Using all 64KB Locations of
External Memory
2512K–AVR–01/10
Since the External Memory is mapped after the Internal Memory as shown in Figure 11,
only 64,928 bytes of External Memory is available by default (address space 0x0000 to
0x025F is reserved for Internal Memory). However, it is possible to take advantage of
the entire External Memory by masking the higher address bits to zero. This can be
done by using the XMMn bits and control by software the most significant bits of the
address. By setting Port C to output 0x00, and releasing the most significant bits for nor-
mal Port Pin operation, the Memory Interface will address 0x0000 - 0x1FFF. See code
example below.
Note:
Care must be exercised using this option as most of the memory is masked away.
Assembly Code Example
C Code Example
#define OFFSET 0x2000
void XRAM_example(void)
{
unsigned char *p = (unsigned char *) (OFFSET + 1);
DDRC = 0xFF;
PORTC = 0x00;
SFIOR = (1<<XMM1) | (1<<XMM0);
*p = 0xaa;
SFIOR = 0x00;
*p = 0x55;
}
; OFFSET is defined to 0x2000 to ensure
; external memory access
; Configure Port C (address high byte) to
; output 0x00 when the pins are released
; for normal Port Pin operation
ldi
out
ldi
out
; release PC7:5
ldi
out
; write 0xAA to address 0x0001 of external
; memory
ldi
sts
; re-enable PC7:5 for external memory
ldi
out
; store 0x55 to address (OFFSET + 1) of
; external memory
ldi
sts
1. See “About Code Examples” on page 7.
r16, 0xFF
DDRC, r16
r16, 0x00
PORTC, r16
r16, (1<<XMM1)|(1<<XMM0)
SFIOR, r16
r16, 0xaa
0x0001+OFFSET, r16
r16, (0<<XMM1)|(0<<XMM0)
SFIOR, r16
r16, 0x55
0x0001+OFFSET, r16
(1)
(1)
ATmega8515(L)
33