PIC16C642-04/SO Microchip Technology, PIC16C642-04/SO Datasheet - Page 27

• Manufacturer Part Number: PIC16C642-04/SO
• Description: IC MCU OTP 4KX14 COMP 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C642-04/SO

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Core Processor: PIC
• Speed: 4MHz
• Peripherals: Brown-out Detect/Reset, LED, POR, WDT
• Number Of I /o: 22
• Program Memory Type: OTP
• Ram Size: 176 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: PIC16C
• No. Of I/o's: 22
• Ram Memory Size: 176Byte
• Cpu Speed: 4MHz
• No. Of Timers: 1
• Processor Series: PIC16C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 176 B
• Interface Type: RS- 232
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 8
• Operating Supply Voltage: 3 V to 6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

4.3
The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is readable and
writable. The high byte (PC<12:8>) is not directly read-
able or writable and comes from PCLATH. On any
reset, the PC is cleared. Figure 4-11 shows the two
situations for the loading of the PC. The upper example
in the figure shows how the PC is loaded on a write to
PCL (PCLATH<4:0>
the figure shows how the PC is loaded during a CALL
or GOTO instruction (PCLATH<4:3>
FIGURE 4-11: LOADING OF PC IN
4.3.1
A computed GOTO is accomplished by adding an
offset to the program counter (ADDWF PCL). When
doing a table read using a computed GOTO method,
care should be exercised if the table location crosses a
PCL memory boundary (each 256 byte block). Refer to
the application note “Implementing a Table Read”
(AN556).
PC
PC
1996 Microchip Technology Inc.
12
12 11 10
2
PCL and PCLATH
COMPUTED GOTO
5
PCH
PCLATH<4:3>
PCH
PCLATH
PCLATH<4:0>
8
PCLATH
8
DIFFERENT SITUATIONS
7
7
PCH). The lower example in
PCL
PCL
11
8
0
0
PCH).
Instruction with
PCL as
Destination
ALU result
GOTO, CALL
Opcode <10:0>
Preliminary
PIC16C64X & PIC16C66X
4.3.2
PIC16C64X & PIC16C66X devices have an 8 level
deep x 13-bit wide hardware stack (Figure 4-2). The
stack space is not part of either program or data space
and the stack pointer is not readable or writable. The
PC is PUSHed onto the stack when a CALL instruction
is executed or an interrupt causes a branch. The stack
is POPed in the event of a RETURN, RETLW or a RETFIE
instruction execution. PCLATH is not affected by a
PUSH or POP operation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
4.4
PIC16C642 and PIC16C662 devices have 4K of pro-
gram memory, but the CALL and GOTO instructions only
have an 11-bit address range. This 11-bit address
range allows a branch within a 2K program memory
page size. To allow CALL and GOTO instructions to
address the entire 4K program memory address range,
there must be another bit to specify the program mem-
ory page. This paging bit comes from the PCLATH<3>
bit (Figure 4-11). When doing a CALL or GOTO instruc-
tion, the user must ensure that this page select bit
(PCLATH<3>) is programmed so that the desired pro-
gram memory page is addressed. If a return from a
CALL instruction (or interrupt) is executed, the entire
13-bit PC is pushed onto the stack. Therefore, manipu-
lation of the PCLATH<3> bit is not required for the
return instructions (which POPs the address from the
stack).
Note:
Note 1: There are no status bits to indicate stack
Note 2: There are no instructions mnemonics
STACK
Program Memory Paging
The PIC16C64X & PIC16C66X ignore the
PCLATH<4> bit, which is used for program
memory pages 2 and 3 (1000h - 1FFFh).
The use of PCLATH<4> as a general pur-
pose read/write bit is not recommended
since this may affect upward compatibility
with future products.
overflow or stack underflow conditions.
called PUSH or POP. These are actions
that occur from the execution of the CALL,
RETURN,
tions, or the vectoring to an interrupt
address.
RETLW, and RETFIE instruc-
DS30559A-page 27