PIC18F65J90-I/PT Microchip Technology, PIC18F65J90-I/PT Datasheet - Page 2

• Manufacturer Part Number: PIC18F65J90-I/PT
• Description: IC PIC MCU FLASH 16KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F65J90-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 51
• Ram Memory Size: 2KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: AUSART, EUSART, I2C, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183030
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F85J90 FAMILY
2. Module: Reset
4.5
The Configuration Mismatch (CM) Reset register is
designed to detect and attempt to recover from
random, memory corrupting events. This includes
Electrostatic Discharge (ESD) events which can cause
widespread, single-bit changes throughout the device
and result in catastrophic failure.
In PIC18FXXXX Flash devices, the device Configura-
tion registers (located in the configuration memory
space) are continuously monitored during operation by
comparing their values to complimentary Shadow
registers. If a mismatch is detected between the two
sets of registers, a CM Reset automatically occurs.
These events are captured by the CM bit (RCON<5>).
Whenever a CM event occurs, this bit is set to ‘0’. For
any other Reset event, this bit does not change.
A CM Reset behaves similarly to a Master Clear Reset,
RESET instruction, WDT time-out or Stack Event
Resets. As with all hard and power Reset events, the
device Configuration Words are reloaded from the
Flash Configuration Words in program memory as the
device restarts.
80286E-page 2
The following section is added after Section 4.4
“Brown-out Reset (BOR)” on page 47.
Configuration Mismatch (CM)
3. Module: Reset
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal
operation. Status bits from the RCON register, CM, RI,
TO, PD, POR and BOR, are set or cleared differently in
different Reset situations, as indicated in Table 4-1.
These bits are used in software to determine the nature
of the Reset.
In the second paragraph of Section 4.6 “Reset
State of Registers”, on page 50, the CM bit is
added to the parenthetical list of RCON register
status bits.
The paragraph is changed as follows, the bold text
indicating the added content:
© 2008 Microchip Technology Inc.