PIC18F65J90-I/PT Microchip Technology, PIC18F65J90-I/PT Datasheet - Page 14

• Manufacturer Part Number: PIC18F65J90-I/PT
• Description: IC PIC MCU FLASH 16KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F65J90-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 51
• Ram Memory Size: 2KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: AUSART, EUSART, I2C, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183030
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F85J90 FAMILY
19. Module: Section 9-5 “PORTD, TRISD and
20. Module: Section 16.3 “SPI Mode” and
80286E-page 14
Note:
On page 118, the content in the third paragraph is
changed. The changed portion is indicated in bold
text in the following section:
Each of the PORTD pins has a weak internal
pull-up. A single control bit can turn off all the
pull-ups. This is performed by clearing bit RDPU
(PORTG<7>). The weak pull-up is automatically
turned off when the port pin is configured as an
output. The pull-ups are disabled on all device
Resets.
In Section 16.3 “SPI Mode” on page 185 and
Section 16.4 “I
ing new note is included to describe the necessary
procedure to disable the MSSP module:
Disabling the MSSP module by clearing
the SSPEN (SSPCON1<5>) bit may not
reset the module. It is recommended to
clear the SSPSTAT, SSPCON1 and
SSPCON2 registers and select the mode
prior to setting the SSPEN bit to enable
the MSSP module.
LATD Registers”
Section 16.4 “I
2
C Mode” on page 194, the follow-
2
C™ Mode”
21. Module: Figure 16-10: I
On page 204,the figure is replaced with the new
timing diagram provided in Figure 16-10.
Timing (Transmission, 7-Bit
Address)
© 2008 Microchip Technology Inc.
2
C™ Slave Mode