PIC18F65J90-I/PT Microchip Technology, PIC18F65J90-I/PT Datasheet - Page 10

• Manufacturer Part Number: PIC18F65J90-I/PT
• Description: IC PIC MCU FLASH 16KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F65J90-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 51
• Ram Memory Size: 2KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: AUSART, EUSART, I2C, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183030
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F85J90 FAMILY
• The values for the Resets and WDT wake-up and
TABLE 4-2:
• Bits 6, 5 and 4 are renamed and the POR/BOR
TABLE 5-3:
80286E-page 10
...
SPBRGH1
BAUDCON1
CCPR1H
...
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Note 1:
SPBRGH1
BAUDCON1
LCDDATA23
Legend:
Note 1:
interrupt are changed in the fourth page of
Table 4-2: Initialization Conditions for All
Registers, as shown by bold text.
value changed in the last page of Table 5-3:
PIC18F85J90 Family Register File Summary, as
shown in bold text.
File Name
Register
2:
3:
4:
5:
2:
3:
4:
5:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
These registers and/or bits are available only on 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset states shown
are for the 80-pin devices.
Alternate names and definitions for these bits when the MSSP module is operating in I
Masking” for details.
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.4.3 “PLL
Frequency Multiplier” for details.
RA6/RA7 and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default
clock source (FOSC2 Configuration bit = 0); otherwise, they are disabled and these bits read as ‘0’.
(2)
Shaded cells indicate conditions do not apply for the designated device.
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
See Table 4-1 for Reset value for specific condition.
Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read as ‘0’.
EUSART Baud Rate Generator High Byte
ABDOVF
S47C3
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
Bit 7
INITIALIZATION CONDITIONS FOR ALL REGISTERS
PIC18F85J90 FAMILY REGISTER FILE SUMMARY
Applicable Devices
RCIDL
S46C3
Bit 6
RXDTP
S45C3
Bit 5
TXCKP
S44C3
Bit 4
Brown-out Reset
Power-on Reset,
0000 0000
0100 0-00
xxxx xxxx
BRG16
S43C3
Bit 3
S42C3
Bit 2
—
RESET Instruction
MCLR Resets
0000 0000
0100 0-00
uuuu uuuu
Stack Resets
WDT Reset
CM Resets
2
C™ Slave mode. See Section 16.4.3.2 “Address
S41C3
WUE
Bit 1
© 2008 Microchip Technology Inc.
ABDEN
S40C3
Bit 0
Wake-up via WDT
uuuu uuuu
uuuu u-uu
uuuu uuuu
0000 0000
0100 0-00
xxxx xxxx
or Interrupt
POR, BOR
Value on
on page
Details
55, 233
55, 232
55, 161