ATMEGA8515-16AU Atmel, ATMEGA8515-16AU Datasheet - Page 147
![IC AVR MCU 8K 16MHZ 5V 44TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
ATMEGA8515-16AU
Manufacturer Part Number
ATMEGA8515-16AU
Description
IC AVR MCU 8K 16MHZ 5V 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA8515-16AU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
16MHz
Interface Type
SPI/USART
Total Internal Ram Size
512Byte
# I/os (max)
35
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
TQFP
Processor Series
ATMEGA8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
35
Number Of Timers
2
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
Package
44TQFP
Family Name
ATmega
Maximum Speed
16 MHz
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA8515-16AU
Manufacturer:
ATMEL
Quantity:
4 500
Part Number:
ATMEGA8515-16AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Receive Compete Flag and
Interrupt
Receiver Error Flags
2512K–AVR–01/10
The USART Receiver has one flag that indicates the Receiver state.
The Receive Complete (RXC) Flag indicates if there are unread data present in the
receive buffer. This flag is one when unread data exist in the receive buffer, and zero
when the receive buffer is empty (i.e., does not contain any unread data). If the Receiver
is disabled (RXEN = 0), the receive buffer will be flushed and consequently the RXC bit
will become zero.
When the Receive Complete Interrupt Enable (RXCIE) in UCSRB is set, the USART
Receive Complete Interrupt will be executed as long as the RXC Flag is set (provided
that global interrupts are enabled). When interrupt-driven data reception is used, the
receive complete routine must read the received data from UDR in order to clear the
RXC Flag, otherwise a new interrupt will occur once the interrupt routine terminates.
The USART Receiver has three Error Flags: Frame Error (FE), Data OverRun (DOR)
and Parity Error (PE). All can be accessed by reading UCSRA. Common for the error
flags is that they are located in the receive buffer together with the frame for which they
indicate the error status. Due to the buffering of the error flags, the UCSRA must be
read before the receive buffer (UDR), since reading the UDR I/O location changes the
buffer read location. Another equality for the error flags is that they can not be altered by
software doing a write to the flag location. However, all flags must be set to zero when
the UCSRA is written for upward compatibility of future USART implementations. None
of the error flags can generate interrupts.
The Frame Error (FE) Flag indicates the state of the first stop bit of the next readable
frame stored in the receive buffer. The FE Flag is zero when the stop bit was correctly
read (as one), and the FE Flag will be one when the stop bit was incorrect (zero). This
flag can be used for detecting out-of-sync conditions, detecting break conditions and
protocol handling. The FE Flag is not affected by the setting of the USBS bit in UCSRC
since the Receiver ignores all, except for the first, stop bits. For compatibility with future
devices, always set this bit to zero when writing to UCSRA.
The Data OverRun (DOR) Flag indicates data loss due to a Receiver buffer full condi-
tion. A Data OverRun occurs when the receive buffer is full (two characters), it is a new
character waiting in the Receive Shift Register, and a new start bit is detected. If the
DOR Flag is set there was one or more serial frame lost between the frame last read
from UDR, and the next frame read from UDR. For compatibility with future devices,
always write this bit to zero when writing to UCSRA. The DOR Flag is cleared when the
frame received was successfully moved from the Shift Register to the receive buffer.
The Parity Error (PE) Flag indicates that the next frame in the receive buffer had a parity
error when received. If parity check is not enabled the PE bit will always be read zero.
For compatibility with future devices, always set this bit to zero when writing to UCSRA.
For more details see “Parity Bit Calculation” on page 140 and “Parity Checker” on page
148.
ATmega8515(L)
147