ATMEGA8L-8PU Atmel, ATMEGA8L-8PU Datasheet - Page 204

IC AVR MCU 8K 8MHZ 3V 28DIP

ATMEGA8L-8PU

Manufacturer Part Number
ATMEGA8L-8PU
Description
IC AVR MCU 8K 8MHZ 3V 28DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA8L-8PU

Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
8MHz
Interface Type
SPI/TWI/USART
Total Internal Ram Size
1KB
# I/os (max)
23
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
6-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Through Hole
Pin Count
28
Package Type
PDIP
Processor Series
ATMEGA8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Minimum Operating Temperature
- 40 C
Controller Family/series
AVR MEGA
No. Of I/o's
23
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
8MHz
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Boot Loader Lock
Bits
204
ATmega8(L)
Figure 102. Memory Sections
Note:
If no Boot Loader capability is needed, the entire Flash is available for application code. The
Boot Loader has two separate sets of Boot Lock Bits which can be set independently. This gives
the user a unique flexibility to select different levels of protection.
The user can select:
See
be set in software and in Serial or Parallel Programming mode, but they can be cleared by a chip
erase command only. The general Write Lock (Lock bit mode 2) does not control the program-
ming of the Flash memory by SPM instruction. Similarly, the general Read/Write Lock (Lock bit
mode 3) does not control reading nor writing by LPM/SPM, if it is attempted.
To protect the entire Flash from a software update by the MCU
To protect only the Boot Loader Flash section from a software update by the MCU
To protect only the Application Flash section from a software update by the MCU
Allow software update in the entire Flash
Table 78 on page 205
1. The parameters in the figure are given in
Boot Loader Flash Section
Boot Loader Flash Section
Application Flash Section
Application Flash Section
Application Flash Section
Application Flash Section
Program Memory
Program Memory
BOOTSZ = '11'
BOOTSZ = '01'
and
(1)
Table 79 on page 205
$0000
End RWW
Start NRWW
End Application
Start Boot Loader
Flashend
$0000
End RWW
Start NRWW
End Application
Start Boot Loader
Flashend
Table 82 on page 213
Boot Loader Flash Section
Boot Loader Flash Section
Application Flash Section
Application Flash Section
for further details. The Boot Lock Bits can
Application flash Section
Program Memory
Program Memory
BOOTSZ = '10'
BOOTSZ = '00'
$0000
End RWW
Start NRWW
End Application
Start Boot Loader
Flashend
$0000
End RWW, End Application
Start NRWW, Start Boot Loader
Flashend
2486Z–AVR–02/11

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