PIC18F8390T-I/PT Microchip Technology, PIC18F8390T-I/PT Datasheet - Page 122

• Manufacturer Part Number: PIC18F8390T-I/PT
• Description: IC PIC MCU FLASH 4KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F8390T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, LCD, POR, PWM, WDT
• Number Of I /o: 66
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SPI, I2C, EUSART, AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 66
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163028
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit
• For Use With: XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPDM163028 - BOARD DEMO PICDEM LCDAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F6390/6490/8390/8490
9.5
PORTE is a 4-bit wide, bidirectional port. The corre-
sponding Data Direction register is TRISE. Setting a
TRISE bit (= 1) will make the corresponding PORTE
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISE bit (= 0)
will make the corresponding PORTE pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register read and write the latched output value for
PORTE.
All pins on PORTE are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
Pins RE6:RE4 are multiplexed with three of the LCD
common drives. I/O port functions are only available on
those PORTE pins, depending on which commons are
active. The configuration is determined by the
LMUX1:LMUX0 control bits (LCDCON<1:0>). The
availability is summarized in Table 9-9.
RE7 is also multiplexed with LCD segment drive
(SEG31) controlled by the LCDSE3<7> bit. I/O port
function is only available when the segment is disabled.
DS39629C-page 120
Note:
Note:
PORTE, TRISE and
LATE Registers
On a Power-on Reset, these pins are
configured as digital inputs.
The pins corresponding to RE2:RE0 of
other PIC18F parts have the function of
LCDBIAS3:LCDBIAS1
corresponding to RE3 of other PIC18F
parts has the function of COM0. These four
pins cannot be used as digital I/O.
and
the
pin
RE7 also can be configured as the alternate peripheral
pin for the CCP2 module. This is done by clearing the
CCP2MX Configuration bit.
TABLE 9-9:
EXAMPLE 9-5:
CLRF
CLRF
MOVLW
MOVWF
LCDCON
<1:0>
00
01
10
11
PORTE
LATE
30h
TRISE
through COM3)
COM0, COM1
COM0, COM1
Active LCD
Commons
and COM2
All (COM0
PORTE PINS AVAILABLE IN
DIFFERENT LCD DRIVE
CONFIGURATIONS
COM0
; Initialize PORTE by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RE<5:4> as inputs
; RE<7:6> as outputs
INITIALIZING PORTE
© 2007 Microchip Technology Inc.
PORTE Available
RE6, RE5, RE4
RE6, RE5
for I/O
None
RE6