PIC16LF1946-I/MR Microchip Technology, PIC16LF1946-I/MR Datasheet - Page 96

• Manufacturer Part Number: PIC16LF1946-I/MR
• Description: MCU 8BIT 14KB FLASH 3.6V 64QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1946-I/MR

• Core Size: 8-Bit
• Program Memory Size: 14KB (8K x 14)
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 17x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Controller Family/series: PIC16LF
• No. Of I/o's: 54
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Processor Series: PIC16LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: MI2C, SPI, EUSART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 5
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 17 Channel
• On-chip Dac: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F/LF1946/47
7.5.4
The PIE3 register contains the interrupt enable bits, as
shown in
REGISTER 7-4:
DS41414B-page 96
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
U-0
—
Register
PIE3 REGISTER
Unimplemented: Read as ‘0’
CCP5IE: CCP5 Interrupt Enable bit
1 = Enables the CCP5 interrupt
0 = Disables the CCP5 interrupt
CCP4IE: CCP4 Interrupt Enable bit
1 = Enables the CCP4 interrupt
0 = Disables the CCP4 interrupt
CCP3IE: CCP3 Interrupt Enable bit
1 = Enables the CCP3 interrupt
0 = Disables the CCP3 interrupt
TMR6IE: TMR6 to PR6 Match Interrupt Enable bit
1 = Enables the TMR6 to PR6 Match interrupt
0 = Disables the TMR6 to PR6 Match interrupt
Unimplemented: Read as ‘0’
TMR4IE: TMR4 to PR4 Match Interrupt Enable bit
1 = Enables the TMR4 to PR4 Match interrupt
0 = Disables the TMR4 to PR4 Match interrupt
Unimplemented: Read as ‘0’
7-4.
R/W-0/0
CCP5IE
PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
R/W-0/0
CCP4IE
R/W-0/0
CCP3IE
Preliminary
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
TMR6IE
R/W-0/0
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
U-0
—
 2010 Microchip Technology Inc.
R/W-0/0
TMR4IE
U-0
—
bit 0