PIC16LF1946-I/MR Microchip Technology, PIC16LF1946-I/MR Datasheet - Page 321

• Manufacturer Part Number: PIC16LF1946-I/MR
• Description: MCU 8BIT 14KB FLASH 3.6V 64QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1946-I/MR

• Core Size: 8-Bit
• Program Memory Size: 14KB (8K x 14)
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 17x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Controller Family/series: PIC16LF
• No. Of I/o's: 54
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Processor Series: PIC16LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: MI2C, SPI, EUSART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 5
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 17 Channel
• On-chip Dac: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FIGURE 25-12:
TABLE 25-8:
 2010 Microchip Technology Inc.
BAUD1CON
BAUD2CON
INTCON
PIE1
PIE4
PIR1
PIR4
RC1REG
RC1STA
RC2REG
RC2STA
SP1BRGL
SP1BRGH
SP2BRGL
SP2BRGH
TX1STA
TX2STA
Legend:
TXx/CKx pin
TXx/CKx pin
(SCKP = 0)
(SCKP = 1)
(Interrupt)
Note:
RXx/DTx
RCxIF bit
CREN bit
RCxREG
SREN bit
bit SREN
Name
Write to
Read
pin
*
Page provides register information.
— = unimplemented locations, read as ‘ 0 ’. Shaded bits are not used for synchronous master reception.
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
‘0’
TMR1GIE
TMR1GIF
ABDOVF
ABDOVF
SPEN
SPEN
CSRC
CSRC
Bit 7
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
GIE
—
—
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
bit 0
RCIDL
RCIDL
ADIE
Bit 6
PEIE
ADIF
RX9
RX9
TX9
TX9
—
—
bit 1
TMR0IE
EUSART1 Baud Rate Generator, High Byte
EUSART2 Baud Rate Generator, High Byte
EUSART1 Baud Rate Generator, Low Byte
EUSART2 Baud Rate Generator, Low Byte
RC2IE
RC2IF
SREN
SREN
TXEN
TXEN
RCIE
RCIF
Bit 5
—
—
EUSART1 Receive Register
EUSART2 Receive Register
bit 2
Preliminary
TX2IE
CREN
CREN
SYNC
SYNC
SCKP
SCKP
TX2IF
Bit 4
INTE
TXIE
TXIF
bit 3
ADDEN
ADDEN
SENDB
SENDB
BRG16
BRG16
SSPIE
SSPIF
IOCIE
Bit 3
—
—
bit 4
PIC16F/LF1946/47
TMR0IF
CCP1IE
CCP1IF
BRGH
BRGH
FERR
FERR
Bit 2
—
—
—
—
bit 5
TMR2IE
TMR2IF
BCL2IE
BCL2IF
OERR
OERR
TRMT
TRMT
WUE
WUE
INTF
Bit 1
bit 6
bit 7
TMR1IE
SSP2IE
TMR1IF
ABDEN
ABDEN
SSP2IF
IOCIF
RX9D
RX9D
TX9D
TX9D
Bit 0
DS41414B-page 321
Register
on Page
302*
302*
309*
309*
309*
309*
308
308
307
307
306
306
94
93
97
98
97
‘0’