DSPIC30F2011-20E/ML Microchip Technology, DSPIC30F2011-20E/ML Datasheet - Page 3
![IC DSPIC MCU/DSP 12K 28QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
DSPIC30F2011-20E/ML
Manufacturer Part Number
DSPIC30F2011-20E/ML
Description
IC DSPIC MCU/DSP 12K 28QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20ISO.pdf
(210 pages)
3.DSPIC30F2011-20ISO.pdf
(14 pages)
4.DSPIC30F2011-20ISO.pdf
(6 pages)
5.DSPIC30F2011-20ISO.pdf
(18 pages)
6.DSPIC30F2011-20IP.pdf
(26 pages)
Specifications of DSPIC30F2011-20E/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
12KB (4K x 24)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
For Use With
DAF30-4 - DEVICE ATP FOR ICE4000
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
35.2
35.2.1
35.2.2
© 2008 Microchip Technology Inc.
Status and Control Registers
SPI1BUF Register
SPI Registers
Section 35. Serial Peripheral Interface (SPI) (Part II)
The SPI module consists of a 16-bit shift register, SPI1SR, used for shifting data in and out, and a
buffer register, SPI1BUF. The control registers, SPI1CON1 and SPI1CON2, configure the module.
Additionally, a status register, SPI1STAT, indicates various status conditions.
The SPI1STAT, SPI1CON1 and SPI1CON2 registers provide the interface to control the
module’s operation. They are shown in detail in Register 35-1, Register 35-2 and Register 35-3.
• SPI1STAT: SPI1 Status and Control Register
• SPI1CON1: SPI1 Control Register 1
• SPI1CON2: SPI1 Control Register 2
SPI1BUF is the SPI1 Data Receive/Transmit register. The SPI1BUF register is actually
comprised of two separate registers: the Transmit Buffer, SPI1TXB, and the Receive Buffer,
SPI1RXB. These two unidirectional, 16-bit registers share the SFR address of SPI1BUF. If a user
application writes data to be transmitted to the SPI1BUF address, internally the data is written to
the SPI1TXB register. Similarly, when the user application reads the received data from
SPI1BUF, internally the data is read from the SPI1RXB register.
This technique double buffers transmit and receive operations and allows continuous data
transfers in the background. Transmission and reception occur simultaneously.
In addition, there is a 16-bit shift register, SPI1SR, that is not memory mapped. It is used for
shifting data in and out of the SPI port.
This status register indicates various status conditions such as Receive Overflow,
Transmit Buffer Full and Receive Buffer Full. This register is also used to specify the
operation of the module during Idle mode and contains a bit that enables and disables
the module.
This control register specifies the clock prescaler, Master/Slave mode, Word/Byte
communication, clock polarity and clock/data pin operation.
This control register enables or disables the framed SPI operation. This register also
specifies the frame synchronization pulse direction, polarity and edge selection.
DS70272B-page 35-3
35