PIC18F45K20-I/P Microchip Technology, PIC18F45K20-I/P Datasheet - Page 400

• Manufacturer Part Number: PIC18F45K20-I/P
• Description: IC PIC MCU FLASH 16KX16 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F45K20-I/P

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 40-DIP (0.600", 15.24mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: CCP/ECCP/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 14-ch x 10-bit
• Package: 40PDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 64 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM240313 - BOARD DEMO 8BIT XLPAC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPDM164124 - KIT STARTER FOR PIC18F4XK20
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F2XK20/4XK20
FIGURE 26-20:
TABLE 26-22: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 26-21:
TABLE 26-23: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS
DS41303G-page 400
120
121
122
125
126
Param
Param.
RC7/RX/DT
RC6/TX/CK
No.
Note:
No.
RC7/RX/DT
Note:
RC6/TX/CK
TckH2dtV SYNC XMIT (MASTER & SLAVE)
Tckrf
Tdtrf
TdtV2ckl
TckL2dtl
pin
Symbol
pin
Symbol
Refer to Figure 26-4 for load conditions.
pin
pin
Refer to Figure 26-4 for load conditions.
Clock High to Data Out Valid
Clock Out Rise Time and Fall Time
(Master mode)
Data Out Rise Time and Fall Time
SYNC RCV (MASTER & SLAVE)
Data Setup before CK  (DT setup time)
Data Hold after CK  (DT hold time)
EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
120
Characteristic
121
Characteristic
125
121
126
Min
10
15
Min
Max
—
122
—
—
—
—
Units
 2010 Microchip Technology Inc.
Max
ns
ns
20
40
20
Units
ns
ns
ns
Conditions
Conditions