ATTINY26L-8SU Atmel, ATTINY26L-8SU Datasheet - Page 60

• Manufacturer Part Number: ATTINY26L-8SU
• Description: ID MCU AVR 2K 5V 8MHZ 20-SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY26L-8SU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Package: 20SOIC
• Device Core: AVR
• Family Name: ATtiny
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 16
• Interface Type: SPI/USI
• On-chip Adc: 11-chx10-bit
• Number Of Timers: 2
• Cpu Family: ATtiny
• Device Core Size: 8b
• Frequency (max): 8MHz
• Total Internal Ram Size: 128Byte
• # I/os (max): 16
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Package Type: SOIC
• Processor Series: ATTINY2x
• Core: AVR8
• Data Ram Size: 128 B
• Maximum Clock Frequency: 8 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• For Use With: ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK505 - ADAPTER KIT FOR 14PIN AVR MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATTINY26L-8SJ; ATTINY26L-8SJ

Timer/Counter
Interrupt Flag Register
– TIFR
60
ATtiny26(L)
• Bit 6 – OCIE1A: Timer/Counter1 Output Compare Interrupt Enable
When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 compare match A, interrupt is enabled. The corresponding interrupt at vector
$003 is executed if a compare match A occurs. The Compare Flag in Timer/Counter1 is set
(one) in the Timer/Counter Interrupt Flag Register.
• Bit 5 – OCIE1B: Timer/Counter1 Output Compare Interrupt Enable
When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 compare match B, interrupt is enabled. The corresponding interrupt at vector
$004 is executed if a compare match B occurs. The Compare Flag in Timer/Counter1 is set
(one) in the Timer/Counter Interrupt Flag Register.
• Bit 4..3 – Res: Reserved Bits
These bits are reserved bits in the ATtiny26(L) and always read as zero.
• Bit 2 – TOIE1: Timer/Counter1 Overflow Interrupt Enable
When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $005) is
executed if an overflow in Timer/Counter1 occurs. The Overflow Flag (Timer1) is set (one) in the
Timer/Counter Interrupt Flag Register – TIFR.
• Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is
executed if an overflow in Timer/Counter0 occurs. The Overflow Flag (Timer0) is set (one) in the
Timer/Counter Interrupt Flag Register – TIFR.
• Bit 0 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny26(L) and always reads as zero.
• Bit 7 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny26(L) and always reads as zero.
• Bit 6 – OCF1A: Output Compare Flag 1A
The OCF1A bit is set (one) when compare match occurs between Timer/Counter1 and the data
value in OCR1A – Output Compare Register 1A. OCF1A is cleared by hardware when executing
the corresponding interrupt handling vector. Alternatively, OCF1A is cleared, after synchroniza-
tion clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE1A, and OCF1A
are set (one), the Timer/Counter1 A Compare Match interrupt is executed.
• Bit 5 – OCF1B: Output Compare Flag 1B
The OCF1B bit is set (one) when compare match occurs between Timer/Counter1 and the data
value in OCR1B – Output Compare Register 1A. OCF1B is cleared by hardware when executing
the corresponding interrupt handling vector. Alternatively, OCF1B is cleared, after synchroniza-
tion clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE1B, and OCF1B
are set (one), the Timer/Counter1 B Compare Match interrupt is executed.
• Bits 4..3 – Res: Reserved Bits
These bits are reserved bits in the ATtiny26(L) and always read as zero.
Bit
$38 ($58)
Read/Write
Initial Value
R
7
–
0
OCF1A
R/W
6
0
OCF1B
R/W
5
0
R
4
–
0
R
3
–
0
TOV1
R/W
2
0
TOV0
R/W
1
0
R
0
–
0
TIFR
1477K–AVR–08/10