PIC16CE625-20I/P Microchip Technology, PIC16CE625-20I/P Datasheet - Page 37
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PIC16CE625-20I/P
Manufacturer Part Number
PIC16CE625-20I/P
Description
IC MCU OTP 2KX14 EE COMP 18DIP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheet
1.PIC16CE623-04P.pdf
(113 pages)
Specifications of PIC16CE625-20I/P
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
13
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
18-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Connectivity
-
7.2
When an external clock input is used for Timer0, it must
meet certain requirements. The external clock
requirement is due to internal phase clock (T
synchronization. Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
7.2.1
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks
(Figure 7-5). Therefore, it is necessary for T0CKI to be
high for at least 2T
and low for at least 2T
20 ns). Refer to the electrical specification of the
desired device.
FIGURE 7-5:
1999 Microchip Technology Inc.
T0CKI
Note 1: Delay from clock input change to Timer0 increment is 3T
External Clock/Prescaler
Output after sampling
External Clock Input or
Prescaler output
Using Timer0 with External Clock
EXTERNAL CLOCK SYNCHRONIZATION
Increment Timer0 (Q4)
2: External clock if no prescaler selected; prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
with
Therefore, the error in measuring the interval between two edges on Timer0 input = ±4T
TIMER0 TIMING WITH EXTERNAL CLOCK
OSC
the
(and a small RC delay of 20 ns)
OSC
(2)
Timer0
internal
(and a small RC delay of
Q1 Q2 Q3 Q4
(3)
phase
clocks
(1)
OSC
Q1 Q2 Q3 Q4
is
T0
)
When a prescaler is used, the external clock input is
divided by the asynchronous ripple-counter type
prescaler so that the prescaler output is symmetrical.
For the external clock to meet the sampling
requirement, the ripple-counter must be taken into
account. Therefore, it is necessary for T0CKI to have a
period of at least 4T
divided by the prescaler value. The only requirement on
T0CKI high and low time is that they do not violate the
minimum pulse width requirement of 10 ns. Refer to
parameters 40, 41 and 42 in the electrical specification
of the desired device.
7.2.2
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the TMR0 is
actually incremented. Figure 7-5 shows the delay from
the external clock edge to the timer incrementing.
OSC
to 7T
Q1 Q2 Q3 Q4
TIMER0 INCREMENT DELAY
T0 + 1
OSC
. (Duration of Q = T
OSC
PIC16CE62X
(and a small RC delay of 40 ns)
Q1 Q2 Q3 Q4
OSC
T0 + 2
OSC
Small pulse
misses sampling
max.
).
DS40182C-page 37