DSPIC30F2011-20E/P Microchip Technology, DSPIC30F2011-20E/P Datasheet - Page 9
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DSPIC30F2011-20E/P
Manufacturer Part Number
DSPIC30F2011-20E/P
Description
IC DSPIC MCU/DSP 12K 18DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20ISO.pdf
(210 pages)
3.DSPIC30F2011-20ISO.pdf
(14 pages)
4.DSPIC30F2011-20ISO.pdf
(6 pages)
5.DSPIC30F2011-20ISO.pdf
(18 pages)
6.DSPIC30F2011-20IP.pdf
(26 pages)
Specifications of DSPIC30F2011-20E/P
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
12KB (4K x 24)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
18-DIP (0.300", 7.62mm)
For Use With
AC30F005 - MODULE SCKT DSPIC30F 18DIP/SOICACICE0202 - ADAPTER MPLABICE 18P 300 MIL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
35.3.2.1
© 2008 Microchip Technology Inc.
Master Mode
Section 35. Serial Peripheral Interface (SPI) (Part II)
In Master mode, the system clock is prescaled and then used as the serial clock. The prescaling
is based on the settings in the PPRE<1:0> (SPI1CON1<1:0>) and SPRE<2:0>
(SPI1CON1<4:2>) bits. The serial clock is output via the SCK1 pin to the slave devices. The
clock pulses are only generated when there is data to be transmitted. For further information,
refer to 35.4 “Master Mode Clock Frequency”. The CKP and CKE bits determine on which
edge of the clock data transmission occurs.
Both data to be transmitted and data received are, respectively, written into or read from the
SPI1BUF register.
The following describes the SPI1 module operation in Master mode:
1.
2.
3.
4.
5.
Note:
Once the module is set up for the Master mode of operation and enabled, data to be
transmitted is written to the SPI1BUF register. The SPITBF (SPI1STAT<1>) bit is set.
The contents of SPI1TXB are moved to the shift register, SPI1SR, and the SPITBF bit is
cleared by the module.
A series of 8/16 clock pulses shifts out 8/16 bits of transmit data from the SPI1SR to the
SDO1 pin and simultaneously shifts in the data at the SDI1 pin into the SPI1SR.
When the transfer is complete, the following events occur:
a)
b)
c)
d)
If the SPIRBF bit is set (receive buffer is full) when the SPI1 module needs to transfer data
from SPI1SR to SPI1RXB, the module will set the SPIROV (SPI1STAT<6>) bit, indicating
an overflow condition.
Data to be transmitted can be written to SPI1BUF by the user application at any time as
long as the SPITBF (SPI1STAT<1>) bit is clear. The write can occur while SPI1SR is
shifting out the previously written data, allowing continuous transmission.
The interrupt flag bit, SPI1IF, is set. SPI1 interrupts can be enabled by setting the
interrupt enable bit, SPI1IE. The SPI1IF flag is not cleared automatically by the
hardware.
When the ongoing transmit and receive operation is completed, the contents of the
SPI1SR register are moved to the SPI1RXB register.
The SPIRBF (SPI1STAT<0>) bit is set by the module, indicating that the receive buf-
fer is full.
Once the SPI1BUF register is read by the user application, the hardware clears the
SPIRBF bit.
The SPI1SR register cannot be written into directly by the user application. All writes
to the SPI1SR register are performed through the SPI1BUF register.
DS70272B-page 35-9
35