DSPIC30F2011-20E/P Microchip Technology, DSPIC30F2011-20E/P Datasheet - Page 20
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DSPIC30F2011-20E/P
Manufacturer Part Number
DSPIC30F2011-20E/P
Description
IC DSPIC MCU/DSP 12K 18DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20ISO.pdf
(210 pages)
3.DSPIC30F2011-20ISO.pdf
(14 pages)
4.DSPIC30F2011-20ISO.pdf
(6 pages)
5.DSPIC30F2011-20ISO.pdf
(18 pages)
6.DSPIC30F2011-20IP.pdf
(26 pages)
Specifications of DSPIC30F2011-20E/P
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
12KB (4K x 24)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
18-DIP (0.300", 7.62mm)
For Use With
AC30F005 - MODULE SCKT DSPIC30F 18DIP/SOICACICE0202 - ADAPTER MPLABICE 18P 300 MIL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
dsPIC30F Family Reference Manual
35.3.4
35.3.5
DS70272B-page 35-20
SPI1 Receive-only Operation
SPI1 Error Handling
Setting the DISSDO control bit (SPI1CON1<11>) disables transmission at the SDO1 pin. This
allows the SPI1 module to be configured for a Receive-only mode of operation. The SDO1 pin
will be controlled by the respective port function if the DISSDO bit is set.
The DISSDO function is applicable to all SPI operating modes.
If a new data word has been shifted into SPI1SR but the previous SPI1BUF contents have not
been read, the SPIROV bit (SPI1STAT<6>) will be set. Any received data in SPI1SR will not be
transferred, and further data reception is disabled until the SPIROV bit is cleared. The SPIROV
bit is not cleared automatically by the module; it must be cleared by the user application.
The SPI1 Interrupt Flag, SPI1IF, is set whenever the SPIROV, SPIRBF (SPI1STAT<0>) or
SPITBF (SPI1STAT<1>) bits are set. The interrupt flag cannot be cleared by hardware and must
be reset in software. The actual SPI1 interrupt is generated only when the corresponding SPI1IE
bit is set in the IEC0 Control register.
© 2008 Microchip Technology Inc.