PIC18F45J10-E/P Microchip Technology, PIC18F45J10-E/P Datasheet - Page 194
![IC PIC MCU FLASH 16KX16 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18F45J10-E/P
Manufacturer Part Number
PIC18F45J10-E/P
Description
IC PIC MCU FLASH 16KX16 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F24J10-ISO.pdf
(368 pages)
3.PIC18F24J10-ISO.pdf
(6 pages)
4.PIC18F24J10-ISO.pdf
(6 pages)
5.PIC18F24J10-ISO.pdf
(12 pages)
6.PIC18LF24J10-ISS.pdf
(32 pages)
Specifications of PIC18F45J10-E/P
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
40-DIP (0.600", 15.24mm)
For Use With
AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180013 - MODULE PLUG-IN 18F45J10 44TQFPAC162067 - HEADER INTRFC MPLAB ICD2 40/28PAC164329 - MODULE SKT FOR 40DIP 18F45J10
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- PIC16F616T-ISL PDF datasheet
- PIC18F24J10-ISO PDF datasheet #2
- PIC18F24J10-ISO PDF datasheet #3
- PIC18F24J10-ISO PDF datasheet #4
- PIC18F24J10-ISO PDF datasheet #5
- PIC18LF24J10-ISS PDF datasheet #6
- Current page: 194 of 368
- Download datasheet (6Mb)
PIC18F45J10 FAMILY
TABLE 16-4:
DS39682E-page 192
INTCON
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
PIR3
PIE3
IPR3
TRISC
TRISD
SSP1BUF
SSP1ADD
SSP1CON1
SSP1CON2
SSP1STAT
SSP2BUF
SSP2ADD
SSP2CON1
SSP2CON2
SSP2STAT
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP module in I
Note 1:
Name
2:
(1)
These registers and/or bits are not implemented on 28-pin devices and should be read as ‘0’.
Alternate names and definitions for these bits when the MSSP module is operating in I
Section 16.4.3.2 “Address Masking” for details.
GIE/GIEH PEIE/GIEL
MSSP1 Receive Buffer/Transmit Register
MSSP1 Address Register (I
MSSP1 Baud Rate Reload Register (I
MSSP2 Receive Buffer/Transmit Register
MSSP2 Address Register (I
MSSP2 Baud Rate Reload Register (I
PSPIE
PSPIP
PSPIF
OSCFIF
OSCFIE
OSCFIP
SSP2IE
SSP2IP
TRISC7
TRISD7
SSP2IF
WCOL
WCOL
GCEN
GCEN
GCEN
GCEN
Bit 7
SMP
SMP
REGISTERS ASSOCIATED WITH I
(1)
(1)
(1)
ACKSTAT
ACKSTAT ADMSK5
ACKSTAT
ACKSTAT ADMSK5
TRISC6
TRISD6
BCL2IF
BCL2IE
BCL2IP
SSPOV
SSPOV
CMIE
CMIP
CMIF
ADIF
ADIE
ADIP
Bit 6
CKE
CKE
TMR0IE
TRISC5
TRISD5
SSPEN
ACKDT
SSPEN
ACKDT
RCIF
RCIE
RCIP
Bit 5
D/A
D/A
2
2
—
—
—
—
—
—
C™ Slave mode).
C Slave mode).
(2)
(2)
ADMSK4
ADMSK4
2
2
TRISC4
TRISD4
ACKEN
ACKEN
INT0IE
C Master mode).
C Master mode).
Bit 4
TXIF
TXIE
TXIP
CKP
CKP
—
—
—
—
—
—
P
P
(2)
(2)
2
C™ OPERATION
ADMSK3
ADMSK3
TRISC3
TRISD3
SSP1IF
SSP1IE
SSP1IP
BCL1IE
BCL1IP
BCL1IF
SSPM3
SSPM3
RCEN
RCEN
RBIE
Bit 3
—
—
—
S
S
(2)
(2)
ADMSK2
ADMSK2
TMR0IF
CCP1IE
CCP1IP
CCP1IF
TRISC2
TRISD2
SSPM2
SSPM2
Bit 2
PEN
R/W
PEN
R/W
—
—
—
—
—
—
(2)
(2)
ADMSK1
ADMSK1
TMR2IE
TMR2IP
TMR2IF
TRISC1
TRISD1
SSPM1
SSPM1
INT0IF
© 2009 Microchip Technology Inc.
RSEN
RSEN
Bit 1
UA
UA
—
—
—
—
—
—
2
C™ mode.
(2)
(2)
2
C Slave mode. See
TMR1IF
TMR1IE
TMR1IP
CCP2IE
CCP2IP
CCP2IF
TRISC0
TRISD0
SSPM0
SSPM0
RBIF
Bit 0
SEN
SEN
SEN
SEN
BF
BF
—
—
—
on Page
Values
Reset
47
49
49
49
49
49
49
49
49
49
50
50
48
48
48
48
48
48
50
50
50
50
48
50
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