PIC18F45J10-E/P Microchip Technology, PIC18F45J10-E/P Datasheet - Page 142
![IC PIC MCU FLASH 16KX16 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18F45J10-E/P
Manufacturer Part Number
PIC18F45J10-E/P
Description
IC PIC MCU FLASH 16KX16 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F24J10-ISO.pdf
(368 pages)
3.PIC18F24J10-ISO.pdf
(6 pages)
4.PIC18F24J10-ISO.pdf
(6 pages)
5.PIC18F24J10-ISO.pdf
(12 pages)
6.PIC18LF24J10-ISS.pdf
(32 pages)
Specifications of PIC18F45J10-E/P
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
40-DIP (0.600", 15.24mm)
For Use With
AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180013 - MODULE PLUG-IN 18F45J10 44TQFPAC162067 - HEADER INTRFC MPLAB ICD2 40/28PAC164329 - MODULE SKT FOR 40DIP 18F45J10
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- PIC16F616T-ISL PDF datasheet
- PIC18F24J10-ISO PDF datasheet #2
- PIC18F24J10-ISO PDF datasheet #3
- PIC18F24J10-ISO PDF datasheet #4
- PIC18F24J10-ISO PDF datasheet #5
- PIC18LF24J10-ISS PDF datasheet #6
- Current page: 142 of 368
- Download datasheet (6Mb)
signals.
PIC18F45J10 FAMILY
15.4.4
In the Half-Bridge Output mode, two pins are used as
outputs to drive push-pull loads. The PWM output signal
is output on the P1A pin, while the complementary PWM
output signal is output on the P1B pin (Figure 15-4). This
mode can be used for half-bridge applications, as shown
in Figure 15-5, or for full-bridge applications where four
power switches are being modulated with two PWM
In Half-Bridge Output mode, the programmable dead-
band delay can be used to prevent shoot-through
current in half-bridge power devices. The value of bits,
PDC<6:0>, sets the number of instruction cycles before
the output is driven active. If the value is greater than
the duty cycle, the corresponding output remains
inactive during the entire cycle. See Section 15.4.6
“Programmable Dead-Band Delay” for more details
of the dead-band delay operations.
Since the P1A and P1B outputs are multiplexed with
the PORTC<2> and PORTD<5> data latches, the
TRISC<2> and TRISD<5> bits must be cleared to
configure P1A and P1B as outputs.
FIGURE 15-5:
DS39682E-page 140
HALF-BRIDGE MODE
Standard Half-Bridge Circuit (“Push-Pull”)
Half-Bridge Output Driving a Full-Bridge Circuit
PIC18F4XJ10
EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS
P1A
P1B
PIC18F4XJ10
P1A
P1B
FET
Driver
FET
Driver
FET
Driver
FET
Driver
FIGURE 15-4:
Note 1: At this time, the TMR2 register is equal to the
P1A
P1B
td = Dead-Band Delay
Load
V+
V-
(2)
(2)
V+
V-
2: Output signals are shown as active-high.
(1)
PR2 register.
Duty Cycle
td
Load
Period
td
HALF-BRIDGE PWM
OUTPUT
© 2009 Microchip Technology Inc.
FET
Driver
FET
Driver
+
V
-
+
V
-
(1)
Period
(1)
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