PIC18F45J10-E/P Microchip Technology, PIC18F45J10-E/P Datasheet - Page 140
![IC PIC MCU FLASH 16KX16 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18F45J10-E/P
Manufacturer Part Number
PIC18F45J10-E/P
Description
IC PIC MCU FLASH 16KX16 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F24J10-ISO.pdf
(368 pages)
3.PIC18F24J10-ISO.pdf
(6 pages)
4.PIC18F24J10-ISO.pdf
(6 pages)
5.PIC18F24J10-ISO.pdf
(12 pages)
6.PIC18LF24J10-ISS.pdf
(32 pages)
Specifications of PIC18F45J10-E/P
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
40-DIP (0.600", 15.24mm)
For Use With
AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180013 - MODULE PLUG-IN 18F45J10 44TQFPAC162067 - HEADER INTRFC MPLAB ICD2 40/28PAC164329 - MODULE SKT FOR 40DIP 18F45J10
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- PIC16F616T-ISL PDF datasheet
- PIC18F24J10-ISO PDF datasheet #2
- PIC18F24J10-ISO PDF datasheet #3
- PIC18F24J10-ISO PDF datasheet #4
- PIC18F24J10-ISO PDF datasheet #5
- PIC18LF24J10-ISS PDF datasheet #6
- Current page: 140 of 368
- Download datasheet (6Mb)
PIC18F45J10 FAMILY
15.4.2
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L register
contains the eight MSbs and the CCP1CON<5:4>
contains the two LSbs. This 10-bit value is represented
by CCPR1L:CCP1CON<5:4>. The PWM duty cycle is
calculated by the following equation:
EQUATION 15-2:
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not copied into
CCPR1H until a match between PR2 and TMR2 occurs
(i.e., the period is complete). In PWM mode, CCPR1H
is a read-only register.
The CCPR1H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM opera-
tion. When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or two bits
of the TMR2 prescaler, the CCP1 pin is cleared. The
maximum PWM resolution (bits) for a given PWM
frequency is given by the following equation:
EQUATION 15-3:
TABLE 15-2:
DS39682E-page 138
Timer Prescaler (1, 4, 16)
PR2 Value
Maximum Resolution (bits)
PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) •
PWM Resolution (max) =
PWM Frequency
PWM DUTY CYCLE
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
T
OSC
• (TMR2 Prescale Value)
log
(
log(2)
2.44 kHz
F
F
PWM
OSC
FFh
16
10
)
bits
9.77 kHz
FFh
10
4
39.06 kHz
15.4.3
The P1M<1:0> bits in the CCP1CON register allow one
of four configurations:
• Single Output
• Half-Bridge Output
• Full-Bridge Output, Forward mode
• Full-Bridge Output, Reverse mode
The Single Output mode is the standard PWM mode
discussed in Section 15.4 “Enhanced PWM Mode”.
The Half-Bridge and Full-Bridge Output modes are
covered in detail in the sections that follow.
The general relationship of the outputs in all
configurations is summarized in Figure 15-2.
Note:
FFh
10
1
If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
PWM OUTPUT CONFIGURATIONS
156.25 kHz
3Fh
1
8
© 2009 Microchip Technology Inc.
312.50 kHz
1Fh
1
7
416.67 kHz
6.58
17h
1
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