PIC16F886-I/SP Microchip Technology, PIC16F886-I/SP Datasheet - Page 196
![IC PIC MCU FLASH 8KX14 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC16F886-I/SP
Manufacturer Part Number
PIC16F886-I/SP
Description
IC PIC MCU FLASH 8KX14 28DIP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.MCP1631RD-MCC2.pdf
(328 pages)
3.PIC16F882-ISS.pdf
(16 pages)
4.PIC16F882-ISS.pdf
(36 pages)
5.PIC16F883-ISO.pdf
(288 pages)
Specifications of PIC16F886-I/SP
Program Memory Type
FLASH
Program Memory Size
14KB (8K x 14)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
24
Eeprom Size
256 x 8
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
368 B
Interface Type
MSSP/EUSART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
24
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM164123, DM164120-3, DV164122
Minimum Operating Temperature
- 40 C
On-chip Adc
11-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM164123 - KIT MANAGEMENT SYSTEM PICDEMDVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F886-I/SP
Manufacturer:
NXP
Quantity:
2 400
PIC16F882/883/884/886/887
13.4.8
Transmission of a data byte, a 7-bit address, or the
other half of a 10-bit address, is accomplished by sim-
ply writing a value to the SSPBUF register. This action
will set the Buffer Full bit, BF, and allow the Baud Rate
Generator to begin counting and start the next trans-
mission. Each bit of address/data will be shifted out
onto the SDA pin after the falling edge of SCL is
asserted (see data hold time specification, parameter
106). SCL is held low for one Baud Rate Generator roll-
over count (T
released high (see data setup time specification,
parameter 107). When the SCL pin is released high, it
is held that way for T
must remain stable for that duration and some hold
time after the next falling edge of SCL. After the eighth
bit is shifted out (the falling edge of the eighth clock),
the BF bit is cleared and the master releases SDA,
allowing the slave device being addressed to respond
with an ACK bit during the ninth bit time, if an address
match occurs, or if data was received properly.
status of ACK is written into the ACKDT bit on the fall-
ing edge of the ninth clock. If the master receives an
Acknowledge, the Acknowledge Status bit, ACKSTAT,
is cleared. If not, the bit is set. After the ninth clock, the
SSPIF bit is set and the master clock (Baud Rate Gen-
erator) is suspended until the next data byte is loaded
into the SSPBUF, leaving SCL low and SDA
unchanged (Figure 13-15).
After the write to the SSPBUF, each bit of the address
will be shifted out on the falling edge of SCL, until all
seven address bits and the R/W bit, are completed. On
the falling edge of the eighth clock, the master will
de-assert the SDA pin, allowing the slave to respond
with an Acknowledge. On the falling edge of the ninth
clock, the master will sample the SDA pin to see if the
address was recognized by a slave. The status of the
ACK bit is loaded into the ACKSTAT Status bit
(SSPCON2 register). Following the falling edge of the
ninth clock transmission of the address, the SSPIF is
set, the BF bit is cleared and the Baud Rate Generator
is turned off, until another write to the SSPBUF takes
place, holding SCL low and allowing SDA to float.
13.4.8.1
In Transmit mode, the BF bit (SSPSTAT register) is set
when the CPU writes to SSPBUF, and is cleared when
all eight bits are shifted out.
13.4.8.2
If the user writes the SSPBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur). WCOL
must be cleared in software.
DS41291D-page 194
I
TRANSMISSION
2
BRG
C™ MASTER MODE
BF Status Flag
WCOL Status Flag
). Data should be valid before SCL is
BRG
. The data on the SDA pin
The
Preliminary
13.4.8.3
In Transmit mode, the ACKSTAT bit (SSPCON2
register) is cleared when the slave has sent an
Acknowledge (ACK = 0), and is set when the slave
does not Acknowledge (ACK = 1). A slave sends an
Acknowledge when it has recognized its address
(including a general call), or when the slave has
properly received its data.
13.4.9
Master mode reception is enabled by programming the
Receive Enable bit, RCEN (SSPCON2 register).
The Baud Rate Generator begins counting, and on
each rollover, the state of the SCL pin changes
(high-to-low/low-to-high) and data is shifted into the
SSPSR. After the falling edge of the eighth clock, the
RCEN bit is automatically cleared, the contents of the
SSPSR are loaded into the SSPBUF, the BF bit is set,
the SSPIF flag bit is set and the Baud Rate Generator
is suspended from counting, holding SCL low. The
MSSP is now in Idle state, awaiting the next command.
When the buffer is read by the CPU, the BF bit is auto-
matically cleared. The user can then send an Acknowl-
edge bit at the end of reception, by setting the
Acknowledge
(SSPCON2 register).
13.4.9.1
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPBUF from SSPSR. It is
cleared when the SSPBUF register is read.
13.4.9.2
In receive operation, the SSPOV bit is set when eight
bits are received into the SSPSR and the BF bit is
already set from a previous reception.
13.4.9.3
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), the WCOL bit is set and the contents of the buffer
are unchanged (the write doesn’t occur).
Note:
The MSSP module must be in an Idle state
before the RCEN bit is set, or the RCEN bit
will be disregarded.
I
2
ACKSTAT Status Flag
C™ MASTER MODE RECEPTION
BF Status Flag
SSPOV Status Flag
WCOL Status Flag
Sequence
© 2007 Microchip Technology Inc.
Enable
bit
ACKEN