ATTINY44A-MU Atmel, ATTINY44A-MU Datasheet - Page 65

• Manufacturer Part Number: ATTINY44A-MU
• Description: IC MCU AVR 4K FLASH 20MHZ 20QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY44A-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 12
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-MLF®, QFN
• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI/USI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 20-ch x 10-bit
• Data Rom Size: 256 B
• A/d Bit Size: 10 bit
• A/d Channels Available: 20
• Height: 0.74 mm
• Length: 4 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Width: 4 mm
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8183C–AVR–03/11
• Port B, Bit 3 – RESET/dW/PCINT11
Table 10-8 on page 65
overriding signals shown in
Table 10-8.
1.
2.
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
• RESET: External Reset input is active low and enabled by unprogramming (“1”) the
• dW: When the debugWIRE Enable (DWEN) Fuse is programmed and Lock bits are
• PCINT11: Pin Change Interrupt source 11. The PB3 pin can serve as an external interrupt
RSTDISBL Fuse. Pullup is activated and output driver and digital input are deactivated when
the pin is used as the RESET pin.
unprogrammed, the debugWIRE system within the target device is activated. The RESET
port pin is configured as a wire-AND (open-drain) bi-directional I/O pin with pull-up enabled
and becomes the communication gateway between target and emulator.
source for pin change interrupt 1.
RSTDISBL is 1 when the Fuse is “0” (Programmed).
DebugWIRE is enabled when DWEN Fuse is programmed and Lock bits are unprogrammed.
PB3/RESET
RSTDISBL
1
RSTDISBL
DEBUGWIRE_ENABLE
Transmit
RSTDISBL
0
0
RSTDISBL
PCINT11 • PCIE1
DEBUGWIRE_ENABLE
PCINT11 • PCIE1)
dW/PCINT11 Input
Overriding Signals for Alternate Functions in PB[3:2]
(1)
(1)
(1)
(1)
/dW/
and
+ DEBUGWIRE_ENABLE
+ DEBUGWIRE_ENABLE
+ DEBUGWIRE_ENABLE
+ DEBUGWIRE_ENABLE
PCINT11
Figure 10-5 on page
Table 10-9 on page 66
(2)
(2)
+ (RSTDISBL
• debugWire
(2)
(2)
(2)
(2)
(1)
58.
+
•
relate the alternate functions of Port B to the
PB2/INT0/OC0A/CKOUT/PCINT10
CKOUT
0
CKOUT
1
CKOUT + OC0A enable
CKOUT • System Clock + CKOUT • OC0A
0
PCINT10 • PCIE1 + INT0
PCINT10 • PCIE1 + INT0
INT0/PCINT10 Input
ATtiny24A/44A/84A
65