ATMEGA328-MUR Atmel, ATMEGA328-MUR Datasheet - Page 36
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ATMEGA328-MUR
Manufacturer Part Number
ATMEGA328-MUR
Description
IC MCU AVR 32K FLASH 32QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA328-MUR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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8.11
8271C–AVR–08/10
System Clock Prescaler
Timer/Counter Oscillator can only be used when the Calibrated Internal RC Oscillator is selected
as system clock source.
Applying an external clock source to TOSC1 can be done if EXTCLK in the ASSR Register is
written to logic one. See
description on selecting external clock as input instead of a 32.768 kHz watch crystal.
The ATmega48A/48PA/88A/88PA/168A/168PA/328/328P has a system clock prescaler, and the
system clock can be divided by setting the
This feature can be used to decrease the system clock frequency and the power consumption
when the requirement for processing power is low. This can be used with all clock source
options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clk
clk
When switching between prescaler settings, the System Clock Prescaler ensures that no
glitches occurs in the clock system. It also ensures that no intermediate frequency is higher than
neither the clock frequency corresponding to the previous setting, nor the clock frequency corre-
sponding to the new setting. The ripple counter that implements the prescaler runs at the
frequency of the undivided clock, which may be faster than the CPU's clock frequency. Hence, it
is not possible to determine the state of the prescaler - even if it were readable, and the exact
time it takes to switch from one clock division to the other cannot be exactly predicted. From the
time the CLKPS values are written, it takes between T1 + T2 and T1 + 2 * T2 before the new
clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the pre-
vious clock period, and T2 is the period corresponding to the new prescaler setting.
To avoid unintentional changes of clock frequency, a special write procedure must be followed
to change the CLKPS bits:
1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in
2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is
not interrupted.
ATmega48A/48PA/88A/88PA/168A/168PA/328/328
ADC
CLKPR to zero.
, clk
CPU
, and clk
FLASH
”Asynchronous Operation of Timer/Counter2” on page 156
are divided by a factor as shown in
”CLKPR – Clock Prescale Register” on page
Table 28-12 on page
323.
for further
377.
I/O
36
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