ATMEGA328-MUR Atmel, ATMEGA328-MUR Datasheet - Page 193

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ATMEGA328-MUR

Manufacturer Part Number
ATMEGA328-MUR
Description
IC MCU AVR 32K FLASH 32QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA328-MUR

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
19.8.3
8271C–AVR–08/10
Asynchronous Operational Range
recovery process is then repeated until a complete frame is received. Including the first stop bit.
Note that the Receiver only uses the first stop bit of a frame.
Figure 19-7 on page 193
of the start bit of the next frame.
Figure 19-7. Stop Bit Sampling and Next Start Bit Sampling
The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop
bit is registered to have a logic 0 value, the Frame Error (FEn) Flag will be set.
A new high to low transition indicating the start bit of a new frame can come right after the last of
the bits used for majority voting. For Normal Speed mode, the first low level sample can be at
point marked (A) in
(B). (C) marks a stop bit of full length. The early start bit detection influences the operational
range of the Receiver.
The operational range of the Receiver is dependent on the mismatch between the received bit
rate and the internally generated baud rate. If the Transmitter is sending frames at too fast or too
slow bit rates, or the internally generated baud rate of the Receiver does not have a similar (see
Table 19-2 on page
frames to the start bit.
The following equations can be used to calculate the ratio of the incoming data rate and internal
receiver baud rate.
Table 1.
D
S
S
S
R
ATmega48A/48PA/88A/88PA/168A/168PA/328/328
F
M
slow
(U2X = 0)
(U2X = 1)
Sample
Sample
RxD
R
slow
Sum of character size and parity size (D = 5 to 10 bit)
Samples per bit. S = 16 for Normal Speed mode and S = 8 for Double Speed
mode.
First sample number used for majority voting. S
for Double Speed mode.
Middle sample number used for majority voting. S
S
is the ratio of the slowest incoming data rate that can be accepted in relation to the
receiver baud rate. R
accepted in relation to the receiver baud rate.
M
=
= 5 for Double Speed mode.
Figure
------------------------------------------ -
S 1
194) base frequency, the Receiver will not be able to synchronize the
1
1
(
D
+
shows the sampling of the stop bit and the earliest possible beginning
2
19-7. For Double Speed mode the first low level must be delayed to
+
D S ⋅
1
)S
3
2
+
S
4
F
fast
5
3
is the ratio of the fastest incoming data rate that can be
6
7
4
8
STOP 1
9
5
10
0/1
(A)
6
R
0/1
F
fast
= 8 for normal speed and S
M
0/1
0/1
(B)
= 9 for normal speed and
=
-----------------------------------
(
D
(
+
D
1
+
)S
2
)S
+
(C)
S
M
F
193
= 4

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