PIC16LF72-I/SS Microchip Technology, PIC16LF72-I/SS Datasheet - Page 32
![IC PIC MCU FLASH 2KX14 28SSOP](/photos/6/81/68119/150-28-ssop_sml.jpg)
PIC16LF72-I/SS
Manufacturer Part Number
PIC16LF72-I/SS
Description
IC PIC MCU FLASH 2KX14 28SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16LF627A-IP.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16F72-ISO.pdf
(136 pages)
4.PIC16F72-ISO.pdf
(136 pages)
Specifications of PIC16LF72-I/SS
Core Size
8-Bit
Program Memory Size
3.5KB (2K x 14)
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Core Processor
PIC
Speed
20MHz
Connectivity
I²C, SPI
Number Of I /o
22
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Controller Family/series
PIC16LF
No. Of I/o's
22
Ram Memory Size
128Byte
Cpu Speed
16MHz
No. Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16LF72-I/SS
Manufacturer:
Microchi
Quantity:
92 666
Part Number:
PIC16LF72-I/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC16F72
5.2
Timer mode is selected by clearing the TMR1CS
(T1CON<1>) bit. In this mode, the input clock to the
timer is F
(T1CON<2>) has no effect, since the internal clock is
always in sync.
5.3
Timer1 may operate in Asynchronous or Synchronous
mode, depending on the setting of the TMR1CS bit.
When Timer1 is being incremented via an external
source, increments occur on a rising edge. After Timer1
is enabled in Counter mode, the module must first have
a falling edge before the counter begins to increment.
FIGURE 5-1:
FIGURE 5-2:
DS39597C-page 30
T1CKI
(Default High)
T1CKI
(Default Low)
Note: Arrows indicate counter increments.
Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.
RC0/T1OSO/T1CKI
RC1/T1OSI
Timer1 Operation in Timer Mode
Timer1 Counter Operation
OSC
/4. The synchronize control bit T1SYNC
Set Flag bit
TMR1IF on
Overflow
TIMER1 INCREMENTING EDGE
TIMER1 BLOCK DIAGRAM
TMR1H
T1OSC
TMR1
TMR1L
Oscillator
Enable
T1OSCEN
(1)
(2)
Clock
Internal
F
OSC
/4
TMR1ON
5.4
Counter mode is selected by setting bit TMR1CS. In
this mode, the timer increments on every rising edge of
clock input on pin RC1/T1OSI when bit T1OSCEN is
set, or on pin RC0/T1OSO/T1CKI when bit T1OSCEN
is cleared.
If T1SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synchro-
nization is done after the prescaler stage. The
prescaler stage is an asynchronous ripple counter.
In this configuration, during SLEEP mode, Timer1 will
not increment even if the external clock is present,
since the synchronization circuit is shut-off. The
prescaler, however, will continue to increment.
On/Off
TMR1CS
1
0
Timer1 Operation in Synchronized
Counter Mode
T1CKPS1:T1CKPS0
T1SYNC
Prescaler
1, 2, 4, 8
0
1
2
© 2007 Microchip Technology Inc.
Synchronized
Clock Input
Synchronize
Q Clock
det