ATTINY88-15MZ Atmel, ATTINY88-15MZ Datasheet - Page 78

• Manufacturer Part Number: ATTINY88-15MZ
• Description: IC MCU AVR 8B 8KB FLASH 32QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY88-15MZ

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.4
11.5
78
Counter Unit
Output Compare Unit
ATtiny88 Automotive
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.
11-2
Figure 11-2. Counter Unit Block Diagram
Signal description (internal signals):
Depending of the mode of operation used, the counter is cleared or incremented at each timer
clock (clk
Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the timer is stopped.
However, the TCNT0 value can be accessed by the CPU, regardless of whether clk
or not. A CPU write overrides (has priority over) all counter clear or count operations.
The counting sequence is determined by the setting of the Clear Timer on Compare Match bit
(CTC0) located in the Timer/Counter Control Register (TCCR0A). For more details about
advanced counting sequences, see
The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by
the CTC0 bit. TOV0 can be used for generating a CPU interrupt.
The 8-bit comparator continuously compares TCNT0 with the Output Compare Registers
(OCR0A and OCR0B). Whenever TCNT0 equals OCR0A or OCR0B, the comparator signals a
match. A match will set the Output Compare Flag (OCF0A or OCF0B) at the next timer clock
cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output
Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is exe-
cuted. Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit
location.
Figure 11-3
shows a block diagram of the counter and its surroundings.
count
clear
clk
top
Tn
T0
DATA BUS
). clk
shows a block diagram of the Output Compare unit.
TCNTn
T0
can be generated from an external or internal clock source, selected by the
Increment or decrement TCNT0 by 1.
Clear TCNT0 (set all bits to zero).
Timer/Counter clock, referred to as clk
Signalize that TCNT0 has reached maximum value.
“Modes of Operation” on page
count
clear
Control Logic
top
TOVn
(Int.Req.)
clk
Tn
79.
Clock Select
T0
( From Prescaler )
Detector
Edge
in the following.
9157B–AVR–01/10
T0
is present
Figure
Tn