ATMEGA88-20MUR Atmel, ATMEGA88-20MUR Datasheet - Page 67

• Manufacturer Part Number: ATMEGA88-20MUR
• Description: MCU AVR 8K FLASH 20MHZ 32QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA88-20MUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: SPI/TWI/USART
• Total Internal Ram Size: 1KB
• # I/os (max): 23
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Package Type: MLF EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.2
13.2.1
2545T–AVR–05/11
Register description
EICRA – External interrupt control register A
The external interrupt control register A contains control bits for interrupt sense control.
• Bit 7..4 – Res: Reserved bits
These bits are unused bits in the Atmel ATmega48/88/168, and will always read as zero.
• Bit 3, 2 – ISC11, ISC10: Interrupt sense control 1 bit 1 and bit 0
The external interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT1 pin that activate the
interrupt are defined in
edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will
generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level
interrupt is selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt.
Table 13-1.
• Bit 1, 0 – ISC01, ISC00: Interrupt sense control 0 bit 1 and bit 0
The external interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the
interrupt are defined in
edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will
generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level
interrupt is selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt.
Table 13-2.
Bit
(0x69)
Read/write
Initial value
ISC11
ISC01
0
0
1
1
0
0
1
1
Interrupt 1 sense control.
Interrupt 0 sense control.
ISC10
ISC00
R
7
–
0
0
1
0
1
0
1
0
1
Table
Table
Description
Description
The low level of INT1 generates an interrupt request
Any logical change on INT1 generates an interrupt request
The falling edge of INT1 generates an interrupt request
The rising edge of INT1 generates an interrupt request
The low level of INT0 generates an interrupt request
Any logical change on INT0 generates an interrupt request
The falling edge of INT0 generates an interrupt request
The rising edge of INT0 generates an interrupt request
R
6
–
0
13-1. The value on the INT1 pin is sampled before detecting
13-2. The value on the INT0 pin is sampled before detecting
R
5
–
0
R
4
–
0
ISC11
R/W
3
0
ISC10
R/W
ATmega48/88/168
2
0
ISC01
R/W
1
0
ISC00
R/W
0
0
EICRA
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