ATMEGA88-20MUR Atmel, ATMEGA88-20MUR Datasheet - Page 168
ATMEGA88-20MUR
Manufacturer Part Number
ATMEGA88-20MUR
Description
MCU AVR 8K FLASH 20MHZ 32QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA88-20MUR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
20MHz
Interface Type
SPI/TWI/USART
Total Internal Ram Size
1KB
# I/os (max)
23
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
32
Package Type
MLF EP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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19.5
19.5.1
2545T–AVR–05/11
Register description
SPCR – SPI control register
• Bit 7 – SPIE: SPI interrupt enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if
the Global Interrupt Enable bit in SREG is set.
• Bit 6 – SPE: SPI enable
When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI
operations.
• Bit 5 – DORD: Data order
When the DORD bit is written to one, the LSB of the data word is transmitted first.
When the DORD bit is written to zero, the MSB of the data word is transmitted first.
• Bit 4 – MSTR: Master/slave select
This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic
zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared,
and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Mas-
ter mode.
• Bit 3 – CPOL: Clock polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low
when idle. Refer to
CPOL functionality is summarized below:
Table 19-3.
• Bit 2 – CPHA: Clock phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or
trailing (last) edge of SCK. Refer to
example. The CPOL functionality is summarized below:
Table 19-4.
Bit
0x2C (0x4C)
Read/write
Initial value
CPOL
CPHA
CPOL functionality.
CPHA Functionality
0
1
0
1
SPIE
R/W
7
0
Figure 19-3 on page 167
SPE
R/W
6
0
DORD
R/W
Figure 19-3 on page 167
5
0
Leading edge
Leading edge
MSTR
Sample
Falling
Rising
R/W
Setup
4
0
and
Figure 19-4 on page 167
CPOL
R/W
3
0
and
CPHA
R/W
ATmega48/88/168
2
0
Figure 19-4 on page 167
SPR1
R/W
1
0
Trailing edge
Trailing edge
Sample
for an example. The
Falling
Rising
Setup
SPR0
R/W
0
0
SPCR
for an
168
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