ATMEGA88-20MUR Atmel, ATMEGA88-20MUR Datasheet - Page 140
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ATMEGA88-20MUR
Manufacturer Part Number
ATMEGA88-20MUR
Description
MCU AVR 8K FLASH 20MHZ 32QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA88-20MUR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
20MHz
Interface Type
SPI/TWI/USART
Total Internal Ram Size
1KB
# I/os (max)
23
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
32
Package Type
MLF EP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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18. 8-bit Timer/Counter2 with PWM and asynchronous operation
18.1
18.2
2545T–AVR–05/11
Features
Overview
•
•
•
•
•
•
•
Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. A simplified
block diagram of the 8-bit Timer/Counter is shown in
I/O pins, refer to
including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca-
tions are listed in the
The PRTIM2 bit in
Timer/Counter2 module.
Figure 18-1. 8-bit timer/counter block diagram.
Single channel counter
Clear timer on compare match (auto reload)
Glitch-free, phase correct pulse width modulator (PWM)
Frequency generator
10-bit clock prescaler
Overflow and compare match interrupt sources (TOV2, OCF2A and OCF2B)
Allows clocking from external 32kHz watch crystal independent of the I/O clock
“Pinout Atmel ATmega48/88/168.” on page
“Minimizing power consumption” on page 41
“Register description” on page
Timer/counter
TCCRnA
OCRnA
TCNTn
OCRnB
=
=
Direction
Count
Clear
Control logic
TOP
=
TCCRnB
BOTTOM
Fixed
value
TOP
clk
153.
=
Tn
0
Figure
18-1. For the actual placement of
ATmega48/88/168
2. CPU accessible I/O Registers,
OCnA
(Int.req.)
OCnB
(Int.req.)
must be written to zero to enable
TOVn
(Int.req.)
Clock select
generation
generation
(From prescaler)
Waveform
Waveform
detector
Edge
OCnA
OCnB
Tn
140
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