AT90USB162-16AUR Atmel, AT90USB162-16AUR Datasheet - Page 88
![IC AVR MCU 16K FLASH 32TQFP](/photos/6/91/69154/313-32-tqfp_sml.jpg)
AT90USB162-16AUR
Manufacturer Part Number
AT90USB162-16AUR
Description
IC AVR MCU 16K FLASH 32TQFP
Manufacturer
Atmel
Series
AVR® 90USBr
Datasheet
1.AT90USB82-16MU.pdf
(307 pages)
Specifications of AT90USB162-16AUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, PS/2, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Processor Series
AT90USBx
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SPI/USART/debugWIRE
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
22
Number Of Timers
2
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATSTK525, ATSTK526, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525
Minimum Operating Temperature
- 40 C
Cpu Family
AT90
Device Core
AVR
Device Core Size
8b
Frequency (max)
16MHz
Total Internal Ram Size
512Byte
# I/os (max)
22
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
32
Package Type
TQFP
For Use With
ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK526 - KIT STARTER FOR AT90USB82/162ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK525 - KIT STARTER FOR AT90USBAT90USBKEY2 - KIT DEMO FOR AT90USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
AT90USB162-16AU
AT90USB162-16AURTR
AT90USB162-16AUTR
AT90USB162-16AUTR
AT90USB162-16AURTR
AT90USB162-16AUTR
AT90USB162-16AUTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT90USB162-16AUR
Manufacturer:
Atmel
Quantity:
2 751
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13. Timer/Counter0 and Timer/Counter1 Prescalers
13.0.1
13.0.2
13.0.3
88
AT90USB82/162
Internal Clock Source
Prescaler Reset
External Clock Source
Timer/Counter0 and 1 share the same prescaler module, but the Timer/Counters can have dif-
ferent prescaler settings. The description below applies to all Timer/Counters. Tn is used as a
general name, n = 0 or 1.
The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This
provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system
clock frequency (f
clock source. The prescaled clock has a frequency of either f
f
The prescaler is free running, i.e., operates independently of the Clock Select logic of the
Timer/Counter, and it is shared by the Timer/Counter Tn. Since the prescaler is not affected by
the Timer/Counter’s clock select, the state of the prescaler will have implications for situations
where a prescaled clock is used. One example of prescaling artifacts occurs when the timer is
enabled and clocked by the prescaler (6 > CSn2:0 > 1). The number of system clock cycles from
when the timer is enabled to the first count occurs can be from 1 to N+1 system clock cycles,
where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execu-
tion. However, care must be taken if the other Timer/Counter that shares the same prescaler
also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is
connected to.
An external clock source applied to the Tn pin can be used as Timer/Counter clock (clk
Tn pin is sampled once every system clock cycle by the pin synchronization logic. The synchro-
nized (sampled) signal is then passed through the edge detector.
equivalent block diagram of the Tn synchronization and edge detector logic. The registers are
clocked at the positive edge of the internal system clock (
high period of the internal system clock.
The edge detector generates one clk
= 6) edge it detects.
Figure 13-1. Tn/T0 Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles
from an edge has been applied to the Tn pin to the counter is updated.
Enabling and disabling of the clock input must be done when Tn has been stable for at least one
system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
CLK_I/O
/1024.
Tn
clk
I/O
CLK_I/O
D
LE
Q
). Alternatively, one of four taps from the prescaler can be used as a
Synchronization
D
Q
Tn
pulse for each positive (CSn2:0 = 7) or negative (CSn2:0
clk
D
CLK_I/O
I/O
). The latch is transparent in the
Q
Figure 13-1
/8, f
CLK_I/O
Edge Detector
/64, f
shows a functional
CLK_I/O
7707F–AVR–11/10
Tn_sync
(To Clock
Select Logic)
Tn
/256, or
). The
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