AT90PWM216-16SUR Atmel, AT90PWM216-16SUR Datasheet
AT90PWM216-16SUR
Specifications of AT90PWM216-16SUR
Related parts for AT90PWM216-16SUR
AT90PWM216-16SUR Summary of contents
Page 1
... Special Microcontroller Features – Low Power Idle, Noise Reduction, and Power Down Modes – Power On Reset and Programmable Brown Out Detection – Flag Array in Bit-programmable I/O Space (4 bytes) 8-bit Microcontroller with 16K Bytes In-System Programmable Flash AT90PWM216 AT90PWM316 7710E–AVR–08/10 ...
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... History Product AT90PWM216 AT90PWM316 2. Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max val- ues will be available after the device is characterized. AT90PWM216/316 2 ADC ADC Analog Input Diff Compar ...
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... Pin Configurations Figure 3-1. Figure 3-2. 7710E–AVR–08/10 SOIC 24-pin Package SOIC 32-pin Package AT90PWM216/316 3 ...
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... Figure 3-3. (PSCIN2/OC1A/MISO_A) PD2 (TXD/DALI/OC0A/SS/MOSI_A) PD3 3.1 Pin Descriptions : Table 3-1. Pin out description S024 Pin SO32 Pin QFN32 Pin Number Number Number AT90PWM216/316 4 QFN32 (7*7 mm) Package. AT9 0PWM316 1 2 (PSCIN1/OC1B) PC1 3 VCC 4 GND 5 (T0/PSCOUT22) PC2 6 (T1/PSCOUT23) PC3 7 (MISO/PSCOUT20) PB0 8 Mnemonic Type ...
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... PC4 AMP1- (Analog Differential Amplifier 1 Input Channel ) ADC9 (Analog Input Channel 9) PC5 I/O AMP1+ (Analog Differential Amplifier 1 Input Channel ) ADC10 (Analog Input Channel 10) PC6 I/O ACMP1 (Analog Comparator 1 Positive Input ) PC7 I/O D2A : DAC output AT90PWM216/316 Name, Function & Alternate Function (2) 5 ...
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... Notes: 4. Overview The AT90PWM216/316 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the AT90PWM216/316 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. ...
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... CISC microcontrollers. The AT90PWM216/316 provides the following features: 16K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512 bytes EEPROM, 1024 bytes SRAM, 53 general purpose I/O lines, 32 general purpose working registers,three Power Stage Controllers, two flex- ...
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... Port C is not available on 24 pins package. Port C also serves the functions of special features of the AT90PWM316 as listed on AT90PWM216/316 8 AT90PWM216 device is available in SOIC 24-pin Package and does not have the D2A (DAC Out- put) brought out to I/0 pins. 67. page 70. ...
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... As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the AT90PWM216/316 as listed on page 4 ...
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... While one instruction is being executed, the next instruc- tion is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory. AT90PWM216/316 10 Block Diagram of the AVR Architecture ...
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... SPI, and other I/O functions. The I/O Memory can be accessed directly the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the AT90PWM216/316 has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. ...
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... The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. AT90PWM216/316 ...
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... R13 R14 R15 R16 R17 … R26 R27 R28 R29 R30 R31 Figure 5-2, each register is also assigned a data memory address, mapping them AT90PWM216/316 Addr. 0x00 0x01 0x02 0x0D 0x0E 0x0F 0x10 0x11 0x1A X-register Low Byte 0x1B X-register High Byte ...
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... Bit Read/Write Initial Value 5.7 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk chip. No internal clock division is used. AT90PWM216/316 14 The X-, Y-, and Z-registers R27 (0x1B ...
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... Register File single clock cycle an ALU Single Cycle ALU Operation T1 clk CPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back for details. AT90PWM216/316 “Memory Program- “Interrupts” on page 55. The list also “ ...
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... When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence.. AT90PWM216/316 16 “Boot Loader Support – Read-While-Write Self-Pro- 266. ...
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... Global Interrupt Enable sleep; enter sleep, waiting for interrupt ; note: will enter sleep before any pending ; interrupt(s) C Code Example _SEI(); /* set Global Interrupt Enable */ _SLEEP(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */ AT90PWM216/316 17 ...
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... Boot Program section and Application Program section. The Flash memory has an endurance of at least 10,000 write/erase cycles. The AT90PWM216/316 Program Counter (PC bits wide, thus addressing the 16K program memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in gramming” ...
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... X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and the 512 bytes of internal data SRAM in the AT90PWM216/316 are all accessible through all these addressing modes. The Register File is described in page 13 ...
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... EEPROM Data Memory The AT90PWM216/316 contains 512 bytes of data EEPROM memory organized as a sep- arate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register ...
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... Read/Write Initial Value • Bits 15..9 – Reserved Bits These bits are reserved bits in the AT90PWM216/316 and will always read as zero. • Bits 8..0 – EEAR8..0: EEPROM Address The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 512 bytes EEPROM space ...
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... EEPROM Master Write Enable will time-out interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail recommended to have the Global Interrupt Flag cleared during all the steps to avoid these problems. AT90PWM216/316 22 EEPROM Mode Bits Programming ...
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... The calibrated Oscillator is used to time the EEPROM accesses. gramming time for EEPROM access from the CPU. Table 6-2. Symbol EEPROM write (from CPU) 7710E–AVR–08/10 EEPROM Programming Time. Number of Calibrated RC Oscillator Cycles 26368 AT90PWM216/316 Table 6-2 lists the typical pro- Typ Programming Time 3 ...
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... EEPROM_write (unsigned int uiAddress, unsigned char ucData Wait for completion of previous write */ while(EECR & (1<<EEWE)) /* Set up address and data registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMWE */ EECR |= (1<<EEMWE); /* Start eeprom write by setting EEWE */ EECR |= (1<<EEWE); } AT90PWM216/316 24 ; 7710E–AVR–08/10 ...
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... Wait for completion of previous write */ while(EECR & (1<<EEWE Set up address register */ EEAR = uiAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from data register */ return EEDR; the EEPROM data can be corrupted because the supply voltage is CC, AT90PWM216/316 reset Protection circuit can CC 25 ...
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... I/O Memory The I/O space definition of the AT90PWM216/316 is shown in All AT90PWM216/316 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions ...
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... General Purpose I/O Register 3– GPIOR3 Bit Read/Write Initial Value 7710E–AVR–08/ GPIOR37 GPIOR36 GPIOR35 GPIOR34 GPIOR33 GPIOR32 GPIOR31 GPIOR30 R/W R/W R/W R AT90PWM216/316 GPIOR3 R/W R/W R/W R ...
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... I/O clock is halted. AT90PWM216/316 28 presents the principal clock systems in the AVR and their distribution. All of the clocks 39. The clock systems are detailed below. Clock Distribution AT90PWM216/316 PSC0/1/2 General I/O ADC Modules CLK ...
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... The Watchdog Oscillator is used for timing this real-time part of the start-up time. The number of WDT Oscillator cycles used for each time-out is shown in 7710E–AVR–08/10 The clock from the selected source is input to the AVR clock generator, and routed to Device Clocking Options Select AT90PWM216/316 AT90PWM216/316 System CKSEL3..0 ...
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... Some initial guidelines for choosing capacitors for use with crystals are given in the manufacturer should be used. For more information on how to choose capacitors and other details on Oscillator operation, refer to the Multi-purpose Oscillator Application Note. Figure 7-2. AT90PWM216/316 30 330. Number of Watchdog Oscillator Cycles = 5.0V) ...
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... The frequency ranges are preliminary values. Actual values are TBD. 2. This option should not be used with crystals, only with ceramic resonators. AT90PWM216/316 Table 7-3. Recommended Range for Capacitors C1 and C2 for Use with Crystals (pF) – ...
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... When this Oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed cali- bration value, see the section AT90PWM216/316 32 Start-up Times for the Oscillator Clock Selection ...
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... If the RSTDISBL fuse is programmed, this start-up time will be increased to 14CK + 4 ensure programming mode can be entered. 2. The device is shipped with this option selected CAL7 CAL6 CAL5 R/W R/W R/W Device Specific Calibration Value AT90PWM216/316 (1)(2) CKSEL3..0 0010 Additional Delay from Reset (V = 5.0V) CC (1) 14CK 14CK + 4.1 ms 14CK + ...
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... Internal PLL for PSC The internal PLL in AT90PWM216/316 generates a clock frequency that is 64x multiplied from nominally 1 MHz input. The source of the 1 MHz PLL input clock is the output of the internal RC Oscillator which is divided down to 1 MHz. See the The PLL is locked on the RC Oscillator and adjusting the RC Oscillator via OSCCAL Register will adjust the fast peripheral clock at the same time ...
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... Read/Write Initial Value • Bit 7..3 – Res: Reserved Bits These bits are reserved bits in the AT90PWM216/316 and always read as zero. • Bit 2 – PLLF: PLL Factor The PLLF bit is used to select the division factor of the PLL. If PLLF is set, the PLL output is 64Mhz. ...
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... The clock will be output also during reset and the normal operation of I/O pin will be overridden when the fuse is pro- grammed. Any clock source, including internal RC Oscillator, can be selected when CLKO AT90PWM216/316 36 External Clock Drive Configuration ...
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... System Clock Prescaler The AT90PWM216/316 system clock can be divided by setting the Clock Prescale Register – CLKPR. This feature can be used to decrease power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals ...
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... Fuse setting. The Application software must ensure that a sufficient division factor is chosen if the selcted clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed. Table 7-10. CLKPS3 AT90PWM216/316 38 Clock Prescaler Select CLKPS2 CLKPS1 ...
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... To avoid the MCU entering the sleep mode unless it is the programmer’s purpose recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up. 7710E–AVR–08/10 Table 8-1 presents the different clock systems in the AT90PWM216/316, and their – ...
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... Reset Time-out period, as described in 8.4 Standby Mode When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down AT90PWM216/316 40 , while allowing the other clocks to run. “Clock Sources” on page , clk ...
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... Active Clock Domains and Wake-up Sources in the Different Sleep Modes. Active Clock Domains (1) 1. Only recommended with external crystal or resonator selected as clock source. 2. Only level interrupt PRPSC2 PRPSC1 PRPSC0 PRTIM1 R/W R/W R AT90PWM216/316 Oscillator s Wake-up Sources ( ( ( PRTIM0 PRSPI ...
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... Refer to “CROSS REFERENCE REMOVED” for details on ADC operation. 8.6.2 Analog Comparator When entering Idle mode, the Analog Comparator should be disabled if not used. When entering ADC Noise Reduction mode, the Analog Comparator should be disabled. In other sleep modes, AT90PWM216/316 42 7710E–AVR–08/10 ...
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... Digital CC page 234 and page 253 for details. AT90PWM216/316 for details on how to configure the Analog “Brown-out Detection” on page 47 ) are stopped, the input buffers of the device will for details on which pins are enabled. If the for details “ ...
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... Reset Sources The AT90PWM216/316 has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length. • ...
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... The Power-on Reset will not work unless the supply voltage has been below V Table 9-1. The POR is activated whenever V rise. The RESET signal is activated again, without any delay, CC decreases below the detection level. CC AT90PWM216/316 DATA BUS MCU Status Register (MCUSR) Circuit Delay Counters Clock ...
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... An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage – V the Time-out period – t Figure 9-4. AT90PWM216/316 46 MCU Start-up, RESET Tied POT V ...
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... Brown-out Detection AT90PWM216/316 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as V ...
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... This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset writing a logic zero to the flag. • Bit 2 – BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset writing a logic zero to the flag. AT90PWM216/316 48 Brown-out Reset During Operation V CC ...
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... Internal Voltage Reference AT90PWM216/316 features an internal bandgap reference. This reference is used for Brown- out Detection. The V from the internal bandgap reference. In order to use the internal Vref necessary to configure it thanks to the REFS1 and REFS0 bits in the ADMUX register and to set an analog feature which requires it ...
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... Watchdog Timer AT90PWM216/316 has an Enhanced Watchdog Timer (WDT). The main features are: • Clocked from separate On-chip Oscillator • 3 Operating modes – Interrupt – System Reset – Interrupt and System Reset • Selectable Time-out period from 16ms to 8s • Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode Figure 9-7 ...
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... Clear WDRF in MCUSR */ MCUSR &= ~(1<<WDRF); /* Write logical one to WDCE and WDE */ /* Keep old prescaler setting to prevent unintentional time-out */ WDTCSR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCSR = 0x00; __enable_interrupt(); 1. The example code assumes that the part specific header file is included. AT90PWM216/316 51 ...
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... WDP bits can result in a time-out when switching to a shorter time-out period; 9.9.1 Watchdog Timer Control Register - WDTCSR Bit Read/Write AT90PWM216/316 52 (1) r16, (1<<WDCE) | (1<<WDE) Got four cycles to set the new values from here - r16, (1<<WDE) | (1<<WDP2) | (1<<WDP0) ...
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... Interrupt Mode 1 0 System Reset Mode Interrupt and System Reset 1 1 Mode x x System Reset Mode 1. For the WDTON Fuse “1” means unprogrammed while “0” means programmed. 54. AT90PWM216/316 Action on Time-out None Interrupt Reset Interrupt, then go to System Reset Mode Reset 0 ...
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... Table 9-6. WDP3 AT90PWM216/316 54 Watchdog Timer Prescale Select Number of WDT Oscillator WDP2 WDP1 WDP0 (2048) cycles (4096) cycles (8192) cycles 16K (16384) cycles 32K (32768) cycles 64K (65536) cycles 128K (131072) cycles 256K (262144) cycles 512K (524288) cycles 1024K (1048576) cycles ...
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... Interrupts AT90PWM216/316. For a general explanation of the AVR interrupt handling, refer to Interrupt Handling” on page 10.1 Interrupt Vectors in AT90PWM216/316 Table 10-1. Vector No 7710E–AVR–08/10 15. Reset and Interrupt Vectors Program Address Source Interrupt Definition External Pin, Power-on Reset, Brown-out Reset, 0x0000 RESET ...
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... When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section. The address of each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash Section. shows reset and Interrupt Vectors placement for the various combinations of Reset and Interrupt Vectors Placement in AT90PWM216/316 IVSEL Reset Address 0 ...
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... When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses in AT90PWM216/316 is: Address Labels Code ...
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... When the BOOTRST Fuse is programmed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses in AT90PWM216/316 is: Address Labels Code ...
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... MCUCR, r16 ; Move interrupts to Boot Flash section ldi r16, (1<<IVSEL) out MCUCR, r16 ret /* Enable change of Interrupt Vectors */ MCUCR = (1<<IVCE); /* Move interrupts to Boot Flash section */ MCUCR = (1<<IVSEL); AT90PWM216/316 “Boot Loader Support – Read-While- for details on Boot Lock bits. 59 ...
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... Refer to the individual module sections for a full description of the alternate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. AT90PWM216/316 60 “Electrical Characteristics(1)” on page 300 Pxn ...
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... I/O CLOCK I/O 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk SLEEP, and PUD are common to all ports. 78, the DDxn bits are accessed at the DDRx I/O address, the AT90PWM216/316 Figure 11 DDxn Q CLR ...
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... This is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. gram of the synchronization when reading an externally applied pin value. The maximum and minimum propagation delays are denoted t AT90PWM216/316 62 summarizes the control signals for the pin value. Port Pin Configurations ...
Page 63
... The out instruction sets the “SYNC LATCH” signal at the positive edge of through the synchronizer is 1 system clock period. pd SYSTEM CLK r16 INSTRUCTIONS out PORTx, r16 SYNC LATCH PINxn r17 AT90PWM216/316 XXX in r17, PINx 0x00 t pd, max t pd, min , a single signal transition on the pin will be delayed 0xFF ...
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... Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the above mentioned sleep modes, as the clamping in these sleep modes produces the requested logic change. AT90PWM216/316 64 (1) r16, (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0) r17, (1< ...
Page 65
... SLEEP, and PUD are common to all ports. All other signals are unique for each pin. summarizes the function of the overriding signals. The pin and port indexes from are not shown in the succeeding tables. The overriding signals are generated internally AT90PWM216/316 Figure 11-2 can be overridden by ...
Page 66
... DI AIO The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details. AT90PWM216/316 66 Generic Description of Overriding Signals for Alternate Functions Full Name Description If this signal is set, the pull-up enable is controlled by the PUOV Pull-up Override signal ...
Page 67
... ADC6 (Analog Input Channel 6) INT2 AMP0+ (Analog Differential Amplifier 0 Input Channel ) AMP0- (Analog Differential Amplifier 0 Input Channel ) ADC5 (Analog Input Channel5 ) INT1 MOSI (SPI Master Out Slave In) PSCOUT21 output MISO (SPI Master In Slave Out) PSCOUT20 output AT90PWM216/316 – – IVSEL IVCE R ...
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... DDB0. When the SPI is enabled as a slave, the data direction of this pin is controlled by DDB0. When the pin is forced input, the pull-up can still be controlled by the PORTB0 and PUD bits. PSCOUT20: Output 0 of PSC 2. AT90PWM216/316 ...
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... SCKin • SPIPS • ICP1B ireset ADC4 ADC7 Overriding Signals for Alternate Functions in PB3..PB0 PB3/AMP0- PB2/ADC5/INT1 AMP0ND ADC5D + In1en 0 In1en INT1 AMP0- ADC5 AT90PWM216/316 PB5/ADC6/ INT2 PB4/AMP0 ADC6D + In2en AMP0ND In2en 0 INT2 ADC6 AMP0+ PB1/MOSI/ PB0/MISO/ PSCOUT21 PSCOUT20 – – ...
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... ADC8/AMP1- – Bit 4 ADC8, Analog to Digital Converter, input channel 8. AMP1-, Analog Differential Amplifier 1 Negative Input Channel. • T1/PSCOUT23 – Bit 3 T1, Timer/Counter1 counter source. PSCOUT23: Output 3 of PSC 2. AT90PWM216/316 70 Port C Pins Alternate Functions Port Pin Alternate Function PC7 D2A : DAC output ...
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... Port C to the overriding signals Figure 11-5 on page 65. Overriding Signals for Alternate Functions in PC7..PC4 PC6/ADC10/ PC7/D2A ACMP1 DAEN DAEN ADC10D 0 0 – ADC10 Amp1 AT90PWM216/316 PC5/ADC9/ PC4/ADC8/ AMP1+ AMP1 – 0 – ADC9D ADC8D 0 0 ADC9 Amp1+ ADC8 Amp1- 71 ...
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... Table 11-8. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO AT90PWM216/316 72 Overriding Signals for Alternate Functions in PC3..PC0 PC3/T1/ PC2/T0/ PSCOUT23 PSCOUT22 PSCen23 PSCen22 1 1 PSCen23 PSCen22 PSCout23 PSCout22 T1 T0 PC1/PSCIN1/ PC0/INT3/ OC1B PSCOUT10 PSCen10 0 1 OC1Ben PSCen10 ...
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... MOSI_A (Programming & alternate SPI Master Out Slave In) PSCIN2 (PSC 2 Digital Input) OC1A (Timer 1 Output Compare A) MISO_A (Programming & alternate Master In SPI Slave Out) PSCIN0 (PSC 0 Digital Input ) CLKO (System Clock Output) PSCOUT00 output XCK (UART Transfer Clock) SS_A (Alternate SPI Slave Select) AT90PWM216/316 Table 11-9. 73 ...
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... DDD2. When the SPI is enabled as a slave, the data direction of this pin is controlled by DDD2. When the pin is forced input, the pull-up can still be controlled by the PORTD2 bit. • PSCIN0/CLKO – Bit 1 PCSIN0, PSC 0 Digital Input. AT90PWM216/316 74 7710E–AVR–08/10 ...
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... PD6/ADC3/ ACMP0 ACMPM/INT0 ACMP0D ADC3D + In0en 0 In0en – INT0 ADC3 ACOMP0 ACMPM AT90PWM216/316 PD5/ADC2/ PD4/ADC1/RXD/ ACMP2 ICP1A/SCK_A RXEN + SPE • 0 MSTR • SPIPS PD4 • 0 PUD RXEN + SPE • 0 MSTR • SPIPS 0 0 SPE • MSTR • 0 SPIPS 0 – ADC2D ADC1D 0 ...
Page 76
... XTAL2/ADC0 – Bit 2 XTAL2: Chip clock Oscillator pin 2. Used as clock pin for crystal Oscillator or Low-frequency crystal Oscillator. When used as a clock pin, the pin can not be used as an I/O pin. ADC0, Analog to Digital Converter, input channel 0. AT90PWM216/316 76 PD3/TXD/OC0A/ PD2/PSCIN2/ SS/MOSI_A OC1A/MISO_A TXEN + SPE • ...
Page 77
... Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 7710E–AVR–08/10 relates the alternate functions of Port E to the overriding signals shown in 65. PE2/ADC0/ XTAL2 ADC0D 0 Osc Output ADC0 AT90PWM216/316 PE0/RESET/ PE1/OC0B OCD OC0Ben 0 OC0B Osc / Clock input Figure 77 ...
Page 78
... Port C Input Pins Address – PINC Bit Read/Write Initial Value 11.4.7 Port D Data Register – PORTD Bit Read/Write Initial Value 11.4.8 Port D Data Direction Register – DDRD Bit Read/Write Initial Value AT90PWM216/316 PORTB7 PORTB6 PORTB5 PORTB4 R/W R/W R/W R/W 0 ...
Page 79
... R/W N/A N/A N/A N – – – – – – – – – – – – AT90PWM216/316 PIND3 PIND2 PIND1 PIND0 R/W R/W R/W R/W N/A N/A N/A N – PORTE2 PORTE1 PORTE0 R R/W R/W R – DDE2 DDE1 DDE0 R R/W R/W R – ...
Page 80
... If enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low. AT90PWM216/316 80 28. The I/O clock is halted in all sleep modes except Idle “Electrical Characteristics(1)” on page 28 ...
Page 81
... When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed R/W R/W R R/W R/W R AT90PWM216/316 INT3 INT2 INT1 R/W R/W R/W R INTF3 INTF2 INTF1 R/W ...
Page 82
... Tn/T0 pin to the counter is updated. Enabling and disabling of the clock input must be done when Tn/T0 has been stable for at least one system clock cycle, otherwise risk that a false Timer/Counter clock pulse is generated. AT90PWM216/316 82 ). Alternatively, one of four taps from the prescaler can be used as a CLK_I/O ) ...
Page 83
... Since the edge detector uses ExtClk clk_I/O clk I/O T0 Synchronization T1 Synchronization clk 1. The synchronization logic on the input pins ( TSM ICPSEL1 – R/W R AT90PWM216/316 (1) Clear T1 Tn/T0) is shown in Figure 13- – – – – /2.5. clk_I/O ...
Page 84
... When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is nor- mally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. AT90PWM216/316 84 Table ICPSEL1 ...
Page 85
... Control Logic direction TOP BOTTOM Timer/Counter TCNTn = = 0 = OCRnx Fixed TOP Values = OCRnx TCCRnA TCCRnB AT90PWM216/316 Figure 14-1. For the actual 8. CPU accessible I/O Registers, 97. must be written to zero to enable TOVn (Int.Req.) Clock Select clk Tn Edge Tn Detector ( From Prescaler ) OCnA (Int.Req.) Waveform OCnA ...
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... TCNT0 for accessing Timer/Counter0 counter value and so on. The definitions in AT90PWM216/316 86 Table 14-1 are also used extensively throughout the document. 7710E–AVR–08/10 ...
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... OCR0A Register. The assignment is depen- dent on the mode of operation. See “Using the Output Compare Unit” on page 113. “Timer/Counter0 and Timer/Counter1 Prescalers” on page DATA BUS count clear TCNTn direction bottom AT90PWM216/316 for details. The compare match 82. TOVn (Int.Req.) Clock Select Edge Detector clk Tn ...
Page 88
... WGM02:0 bits and Compare Output mode (COM0x1:0) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation Figure 14-3 AT90PWM216/316 88 Increment or decrement TCNT0 by 1. Select between increment and decrement. ...
Page 89
... OCR0x value, the compare match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is downcounting. 7710E–AVR–08/10 DATA BUS OCRnx = (8-bit Comparator ) top bottom Waveform Generator FOCn WGMn1:0 AT90PWM216/316 TCNTn OCFnx (Int.Req.) OCnx COMnx1:0 89 ...
Page 90
... The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM modes. For all modes, setting the COM0x1 tells the Waveform Generator that no action on the OC0x Register performed on the next compare match. For compare output actions in the AT90PWM216/316 90 COMnx1 Waveform ...
Page 91
... TCNT0 and OCR0A, and then counter (TCNT0) is cleared. 7710E–AVR–08/10 Table 14-2 on page 97. For fast PWM mode, refer to Table 14-4 on page 90.). “Timer/Counter Timing Diagrams” on page Figure AT90PWM216/316 Table 14-3 on 98. 95. 14-5. The counter value (TCNT0) 91 ...
Page 92
... In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast AT90PWM216/316 92 1 ...
Page 93
... The TCNT0 value is in the timing diagram shown as a his Table 14-6 on page 98). The actual OC0x value will only be visible on the f clk_I ----------------- - OCnxPWM N 256 = f OC0 AT90PWM216/316 OCRnx Interrupt Flag Set OCRnx Update and TOVn Interrupt Flag Set (COMnx1 (COMnx1 ⋅ /2 when OCR0A is set to zero. This clk_I/O 93 ...
Page 94
... In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A0 bits to AT90PWM216/316 94 14-7. The TCNT0 value is in the timing diagram shown as a histogram for illustrating ...
Page 95
... Figure 14-8 contains timing data for basic Timer/Counter operation. The figure I/O Tn /1) I/O MAX - 1 shows the same timing data, but with the prescaler enabled. AT90PWM216/316 99). The actual OC0x value will only be f clk_I/O = ----------------- - ⋅ N 510 OCnx has a transition from high to low even though Figure 14-7 ...
Page 96
... PWM mode where OCR0A is TOP. Figure 14-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- clk clk (clk I/O TCNTn (CTC) OCRnx OCFnx AT90PWM216/316 96 I/O Tn /8) MAX - 1 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC I/O Tn /8) ...
Page 97
... Clear OC0A on Compare Match, set OC0A at TOP 1 Set OC0A on Compare Match, clear OC0A at TOP 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com- pare Match is ignored, but the set or clear is done at TOP. See for more details. AT90PWM216/316 COM0B0 – ...
Page 98
... Table 14-6 mode. Table 14-6. COM0B1 Note: AT90PWM216/316 98 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase cor- Compare Output Mode, Phase Correct PWM Mode COM0A0 Description 0 Normal port operation, OC0A disconnected. WGM02 = 0: Normal Port Operation, OC0A Disconnected. ...
Page 99
... Note: • Bits 3, 2 – Res: Reserved Bits These bits are reserved bits in the AT90PWM216/316 and will always read as zero. • Bits 1:0 – WGM01:0: Waveform Generation Mode Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting ...
Page 100
... OCR0B as TOP. The FOC0B bit is always read as zero. • Bits 5:4 – Res: Reserved Bits These bits are reserved bits in the AT90PWM216/316 and will always read as zero. • Bit 3 – WGM02: Waveform Generation Mode See the description in the • Bits 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter ...
Page 101
... Timer/Counter Interrupt Mask Register – TIMSK0 Bit Read/Write Initial Value • Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the AT90PWM216/316 and will always read as zero. 7710E–AVR–08/10 Clock Select Bit Description (Continued) CS01 CS00 Description ...
Page 102
... Initial Value • Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the AT90PWM216/316 and will always read as zero. • Bit 2 – OCF0B: Timer/Counter 0 Output Compare B Match Flag The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in OCR0B – ...
Page 103
... The PRTIM1 bit in Timer/Counter1 module. 7710E–AVR–08/10 “Pin Descriptions” on page “16-bit Timer/Counter Register Description” on page “Power Reduction Register” on page 41 AT90PWM216/316 Figure 15-1. For the actual 4. CPU accessible I/O Registers, 124. must be written to zero to enable 103 ...
Page 104
... The double buffered Output Compare Registers (OCRnx) are compared with the Timer/Counter value at all time. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pin (OCnx). Units” on page 112. which can be used to generate an Output Compare interrupt request. AT90PWM216/316 104 Count Clear Control Logic ...
Page 105
... The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF the value stored in the OCRnA or ICRn Register. The assignment is dependent of the mode of operation. AT90PWM216/316 105 ...
Page 106
... Timer Regis- ters, then the result of the access outside the interrupt will be corrupted. Therefore, when both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access. AT90PWM216/316 106 (1) (1) 1. The example code assumes that the part specific header file is included. For I/O Registers located in extended I/O map, “ ...
Page 107
... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. AT90PWM216/316 107 ...
Page 108
... The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CSn2:0) bits located in the Timer/Counter control Register B (TCCRnB). For details on clock sources and prescaler, see AT90PWM216/316 108 (1) (1) 1. The example code assumes that the part specific header file is included. For I/O Registers located in extended I/O map, “ ...
Page 109
... Signalize that TCNTn has reached minimum value (zero). ). The clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear “16-bit Timer/Counter1 with PWM” on page AT90PWM216/316 TOVn (Int.Req.) Clock Select Edge Detector clk Tn Control Logic ( From Prescaler ) TOP ...
Page 110
... When the CPU reads the ICRnH I/O location it will access the TEMP Register. The ICRn Register can only be written when using a Waveform Generation mode that utilizes the ICRn Register for defining the counter’s TOP value. In these cases the Waveform Genera- AT90PWM216/316 110 DATA BUS TEMP (8-bit) ...
Page 111
... I/O bit location). For measuring frequency only, the clearing of the ICFn Flag is not required (if an interrupt handler is used). 7710E–AVR–08/10 105. 82). The edge detector is also identical. However, when the noise canceler is AT90PWM216/316 “Accessing 16-bit Registers” (Figure 13- 111 ...
Page 112
... Register to either TOP or BOTTOM of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the out- put glitch-free. AT90PWM216/316 112 (See “16-bit Timer/Counter1 with PWM” on page shows a block diagram of the Output Compare unit. The small “n” in the register and ...
Page 113
... COMnx1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers 7710E–AVR–08/10 105. AT90PWM216/316 “Accessing 16-bit Registers” Figure 15-5 shows a simplified ...
Page 114
... PWM refer to page 125. A change of the COMnx1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOCnx strobe bits. AT90PWM216/316 114 Waveform D Generator D ...
Page 115
... The timing diagram for the CTC mode is shown in increases until a compare match occurs with either OCRnA or ICRn, and then counter (TCNTn) is cleared. 7710E–AVR–08/10 AT90PWM216/316 113.) “Timer/Counter Timing Diagrams” on page Figure 15-6. The counter value (TCNTn) 122 ...
Page 116
... PWM modes that use dual-slope operation. This high fre- quency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capaci- tors), hence reduces total system cost. AT90PWM216/316 116 1 2 ...
Page 117
... The OCRnA Register however, is double buffered. This feature allows the OCRnA I/O location 7710E–AVR–08/10 ( log TOP R = ---------------------------------- - FPWM log AT90PWM216/316 ) Figure 15-7. The figure OCRnx/TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnx1 (COMnx1 ...
Page 118
... However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to AT90PWM216/316 118 Table on page f ...
Page 119
... TOP actively while the Timer/Counter is running in the phase correct mode can result in an unsymmetrical output. The reason for this can be found in the time of update of the OCRnx Reg- ister. Since the OCRnx update occurs at TOP, the PWM period starts and ends at TOP. This 7710E–AVR–08/10 AT90PWM216/316 ( ) log ...
Page 120
... OCRnx Register is updated by the OCRnx Buffer Register, (see 8 and Figure The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and AT90PWM216/316 120 f OCnxPCPWM 15-9). Table on page ...
Page 121
... R = ---------------------------------- - PFCPWM Figure 15-9. The figure shows phase and frequency correct shows the output generated is, in contrast to the phase correct mode, symmetri- AT90PWM216/316 ( ) + 1 TOP log OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx/TOP Updateand TOVn Interrupt Flag Set ...
Page 122
... Flags are set, and when the OCRnx Register is updated with the OCRnx buffer value (only for modes utilizing double buffering). Figure 15-10. Timer/Counter Timing Diagram, Setting of OCFnx, no Prescaling (clk TCNTn OCRnx OCFnx Figure 15-11 AT90PWM216/316 122 f OCnxPFCPWM Figure 15-10 clk I/O clk ...
Page 123
... FPWM) TCNTn TOP - 1 TOVn (FPWM) and ICFn (if used as TOP) OCRnx Old OCRnx Value (Update at TOP) shows the same timing data, but with the prescaler enabled. AT90PWM216/316 OCRnx OCRnx + 1 OCRnx Value TOP BOTTOM TOP TOP - 1 New OCRnx Value /8) clk_I/O OCRnx + 2 ...
Page 124
... OCnA or OCnB pin must be set in order to enable the output driver. When the OCnA or OCnB is connected to the pin, the function of the COMnx1:0 bits is depen- dent of the WGMn3:0 bits setting. WGMn3:0 bits are set to a Normal or a CTC mode (non-PWM). Table 15-2. COMnA1/COMnB1 AT90PWM216/316 124 clk I/O clk Tn ...
Page 125
... A special case occurs when OCRnA/OCRnB equals TOP and COMnA1/COMnB1 is set. “Phase Correct PWM Mode” on page 118. Table 15-5. Modes of operation supported by the Timer/Counter AT90PWM216/316 (1) Description Normal port operation, OCnA/OCnB disconnected. WGMn3 15: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). ...
Page 126
... When a capture is triggered according to the ICESn setting, the counter value is copied into the Input Capture Register (ICRn). The event will also set the Input Capture Flag (ICFn), and this can be used to cause an Input Capture Interrupt, if this interrupt is enabled. AT90PWM216/316 126 (1) WGMn0 ...
Page 127
... I clk /256 (From prescaler) I clk /1024 (From prescaler) I External clock source on Tn pin. Clock on falling edge External clock source on Tn pin. Clock on rising edge FOC1A FOC1B – R/W R AT90PWM216/316 – – – – Figure 0 – TCCR1C R 0 127 ...
Page 128
... CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. 15.10.7 Input Capture Register 1 – ICR1H and ICR1L Bit Read/Write Initial Value AT90PWM216/316 128 TCNT1[15:8] TCNT1[7:0] ...
Page 129
... Initial Value • Bit 7, 6 – Res: Reserved Bits These bits are unused bits in the AT90PWM216/316, and will always read as zero. • Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt Vector (see “ ...
Page 130
... Initial Value • Bit 7, 6 – Res: Reserved Bits These bits are unused bits in the AT90PWM216/316, and will always read as zero. • Bit 5 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the WGMn3 used as the TOP value, the ICF1 Flag is set when the coun- ter reaches the TOP value ...
Page 131
... Zero crossing retriggering • Demagnetization retriggering • Fault input The PSC can be chained and synchronized to provide a configuration to drive three half bridges. Thanks to this feature it is possible to generate a three phase waveforms for applications such as Asynchronous or BLDC motor drive. 7710E–AVR–08/10 AT90PWM216/316 131 ...
Page 132
... The PSC is seen as two symetrical entities. One part named part A which generates the output PSCOUTn0 and the second one named part B which generates the PSCOUTn1 output. Each part has its own PSC Input Module to manage selected input. AT90PWM216/316 132 PSC Counter ...
Page 133
... Part A PSC Input = Module A OCRnRA Waveform = Generator A OCRnSA Part B PICRn PCNFn PFRCnB PCTLn PFRCnA (See “Output Matrix” on page AT90PWM216/316 PSCOUTn3 POS23 PSCOUTn1 ( From Analog Comparator n Ouput ) PSCn Input B Output PISELnB Matrix PSCn Input A PSCINn PISELnA PSCOUTn2 POS22 PSCOUTn0 POM2(PSC2 only) PSOCn 159 ...
Page 134
... Signal Description Figure 16-3. PSC External Block View Note: 16.4.1 Input Description Table 16-1. Name OCRnRB[1 1:0] OCRnSB[1 1:0] OCRnRA[1 1:0] OCRnSA[1 1:0] AT90PWM216/316 134 CLK PLL CLK I/O SYnIn StopOut 12 OCRnRB[11:0] 12 OCRnSB[11:0] 12 OCRnRA[11:0] 12 OCRnSA[11:0] 4 OCRnRB[15:12] (Flank Width Modulation) 12 PICRn[11:0] ...
Page 135
... Counter value at retriggering event PSC Interrupt Request : three souces, overflow, fault, and input capture ADC Synchronization (+ Amplifier Syncho. ) Stop Output (for synchronized mode) 1. See Figure 16-38 on page 160 2. See “Analog Synchronization” on page 159. AT90PWM216/316 Type Width Register 4 bits Signal Signal (1) Signal ...
Page 136
... Ramps illustrate the output of the PSC counter included in the waveform generators. Centered Mode is like a one ramp mode which count down up and down. Notice that the update of a new set of values is done regardless of ramp Mode at the top of the last ramp. AT90PWM216/316 136 PSC Cycle Sub-Cycle A ...
Page 137
... One moment for PSCn0 description with OT0 which gives the time of the whole moment One moment for PSCn1 description with OT1 which gives the time of the whole moment 7710E–AVR–08/10 OCRnRA OCRnSA 0 On-Time 0 Dead-Time 0 PSC Cycle Minimal value for Dead-Time 0 and Dead-Time 1/Fclkpsc AT90PWM216/316 OCRnRB OCRnSB 0 On-Time 1 Dead-Time 1 137 ...
Page 138
... Dead-Time 1 values with : On-Time 0 = (OCRnRAH/L - OCRnSAH/L) * 1/Fclkpsc On-Time 1 = (OCRnRBH/L - OCRnSBH/L) * 1/Fclkpsc Dead-Time 0 = (OCRnSAH 1/Fclkpsc Dead-Time 1 = (OCRnSBH 1/Fclkpsc Note: 16.5.2.3 One Ramp Mode In One Ramp mode, PSCOUTn0 and PSCOUTn1 outputs can overlap each other. AT90PWM216/316 138 OCRnRA OCRnSA OCRnSB 0 0 On-Time 0 Dead-Time 0 ...
Page 139
... Dead-Time 0 = (OCRnSAH 1/Fclkpsc Dead-Time 1 = (OCRnSBH/L - OCRnRAH/L) * 1/Fclkpsc Note: 16.5.2.4 Center Aligned Mode In center aligned mode, the center of PSCn00 and PSCn01 signals are centered. 7710E–AVR–08/10 OCRnRA OCRnSA 0 On-Time 0 Dead-Time 0 PSC Cycle Minimal value for Dead-Time 0 = 1/Fclkpsc AT90PWM216/316 OCRnRB OCRnSB On-Time 1 Dead-Time 1 139 ...
Page 140
... OCRnRAH/L is not used to control PSC Output waveform timing. Nevertheless, it can be useful to adjust ADC synchronization ( Figure 16-10. Run and Stop Mechanism in Centered Mode OCRnR B OCRnSB OCRnSA PSC C o unter Run PSCOUT n0 PSCOUT n1 Note: AT90PWM216/316 140 PSC Counter OCRnRB OCRnSB OCRnSA 0 On-Time 0 On-Time 1 PSCOUTn0 PSCOUTn1 ...
Page 141
... Cycles are grouped into frames of 16 cycles. Cycles are modulated by a sequence given by the 7710E–AVR–08/10 Regulation Loop Writting in Calculation PSC Registers Cycle Cycle Cycle Cycle With Set i With Set i With Set i With Set i page AT90PWM216/316 Request for an Update Cycle With Set j End of Cycle 164. 141 ...
Page 142
... In enhanced mode, the output frequency is the average of the frame formed by the 16 consecu- tive cycles. f and f b1 Then the frequency resolution is divided by 16. In the example above, the resolution equals 25 Hz. AT90PWM216/316 142 Δ – = period in a PSC cycle and is given by the following formula: PSC is the output operating frequency ...
Page 143
... Figure 16-12. Resulting Frequency versus 7710E–AVR–08/10 and f where the nearest base frequency below the wanted frequency. The number Distribution the modulated frame b2 PWM - cycle prime cycle corresponding cycle AT90PWM216/316 is the nearest base frequency above the wanted The f and f frequencies are evenly distrib ...
Page 144
... Figure 16-13. Enhanced Mode, Timing Diagram DT0 OT0 PSCOUTn0 PSCOUTn1 Period The supplementary step in counting to generate f in the frame according to the fractional divider. lated frame,” on page The waveform frequency is defined by the following equations the fractionel divider factor. AT90PWM216/316 144 ----------------------------- - = ---------------------------------------------------------------------- ( PSCn PSCnCycle ...
Page 145
... Digital 1 Filter 1 PFLTEnA CLK PSC (PFLTEnB) PISELnA (PISELnB) PELEVnA / PCAEnA 2 (PELEVnB) (PCAEnB) 4 PRFMnA3:0 (PRFMnB3:0) CLK PSC CLK PSC AT90PWM216/316 16.25.14page 169), PSCnIN0/1 input can act Input Processing (retriggering ...) PSC Core Output (Counter, Control PSCOUTn0 Waveform (PSCOUTn1) Generator, ...) (PSCOUT22) (PSCOUT23) 145 ...
Page 146
... The polarity of PSCn Input B is configurable thanks to a sense control block. PSCn Input B can be configured to do not act or to act on level or edge modes. PSCn Input B can be the Output of the analog comparator or the PSCINn input. As the period of the cycle decreases, the instantaneous frequency of the two outputs increases. AT90PWM216/316 146 On-Time 0 Dead-Time 0 Dead-Time 1 This example is given in “ ...
Page 147
... This example is given in “Input Mode 1” in “ ramp mode” See Figure 16-20. for details. On level mode, it’s possible to use PSC to generate burst by using Input Mode 3 or Mode 4 ( See Figure 16-24. and Figure 16-25. for details.) AT90PWM216/316 On-Time 1 Dead-Time 0 On-Time 1 Dead-Time 1 ...
Page 148
... Signal Polarity One can select the active edge (edge modes) or the active level (level modes) See PELEVnx bit description in Section “PSC n Input A Control Register – PFRCnA”, page 16916.25.14. AT90PWM216/316 148 OFF BURST is running. So thanks to PSC Asynchronous Output Control bit ...
Page 149
... See “PSC Input Mode 9: Fixed Frequency Edge Retrigger PSC” on page 1001b 155. Reserved : Do not use 1010b 1011b 1100b 1101b See “PSC Input Mode 14: Fixed Frequency Edge Retrigger PSC and 1110b Disactivate Output” on page 156. Reserved : Do not use 1111b AT90PWM216/316 149 ...
Page 150
... PSC Input B is take into account during DT1 and OT1 only. It has no effect during DT0 and OT0. When PSC Input B event occurs, PSC releases PSCOUTn1, waits for PSC Input B inactive state and then jumps and executes DT0 plus OT0. AT90PWM216/316 150 DT0 ...
Page 151
... PSC Input B inactive state. Even if PSC Input B is released during DT0 or OT0, DT0 plus OT0 sub-cycle is always com- pletely executed. 7710E–AVR–08/10 DT0 OT0 DT1 OT1 OT1 DT0 OT0 DT1 OT1 OT1 AT90PWM216/316 DT0 OT0 DT1 DT0 OT0 DT1 OT1 OT1 151 ...
Page 152
... When PSC Input B event occurs, PSC releases PSCnOUT1, jumps and executes DT0 plus OT0 plus DT1 while PSC Input active state. Even if PSC Input B is released during DT0 or OT0, DT0 plus OT0 sub-cycle is always com- pletely executed. 16.12 PSC Input Mode 4: Deactivate outputs without changing timing. AT90PWM216/316 152 DT0 OT0 DT1 DT1 OT1 ...
Page 153
... Used in Fault mode 5, PSCn Input A or PSCn Input B act indifferently on On-Time0/Dead-Time0 or on On-Time1/Dead-Time1. 7710E–AVR–08/10 DT1 OT1 DT0 OT0 OT0 DT1 OT1 DT0 OT0 DT0 OT0 DT1 OT1 AT90PWM216/316 DT1 OT1 DT0 OT0 DT1 DT1 OT1 DT0 OT0 DT1 DT0 OT0 DT1 OT1 ...
Page 154
... PSCOUTn1 PSCn Input A or PSCn Input B Note: Used in Fault mode 7, PSCn Input A or PSCn Input B act indifferently on On-Time0/Dead-Time0 or on On-Time1/Dead-Time1. 16.16 PSC Input Mode 8: Edge Retrigger PSC AT90PWM216/316 154 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 1. Software action is the setting of the PRUNn bit in PCTLn register. ...
Page 155
... Note: In one ramp mode, the retrigger event on input A resets the whole ramp. So the PSC doesn’t jump to the opposite dead-time. 16.17 PSC Input Mode 9: Fixed Frequency Edge Retrigger PSC 7710E–AVR–08/10 DT0 OT0 DT1 DT1 OT1 OT1 DT0 OT0 DT1 DT1 OT1 OT1 AT90PWM216/316 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 155 ...
Page 156
... Figure 16-34. PSC behaviour versus PSCn Input B in Mode 9 DT0 OT0 PSCOUTn0 PSCOUTn1 PSCn Input B The retrigger event is taken into account only if it occurs during the corresponding On-Time. 16.18 PSC Input Mode 14: Fixed Frequency Edge Retrigger PSC and Disactivate Output AT90PWM216/316 156 DT0 OT0 DT1 DT1 OT1 DT0 ...
Page 157
... OT1 OT1 Available Input Modes according to Running Modes 1 Ramp Mode 2 Ramp Mode Valid Valid Do not use Valid Do not use Valid Valid Valid Do not use Valid AT90PWM216/316 DT0 OT0 DT0 OT0 DT1 OT1 DT0 OT0 DT0 OT0 DT1 OT1 4 Ramp Mode Valid ...
Page 158
... Even though the Input Capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. AT90PWM216/316 158 Available Input Modes according to Running Modes 1 Ramp Mode ...
Page 159
... Analog Synchronization PSC generates a signal to synchronize the sample and hold; synchronisation is mandatory for measurements. 7710E–AVR–08/10 Output Matrix versus ramp number Ramp 0 Ramp 1 POMV2A0 POMV2A1 POMV2B0 POMV2B1 Output Matrix AT90PWM216/316 Ramp 2 Ramp 3 POMV2A2 POMV2A3 POMV2B2 POMV2B3 PSCOUT20 0 PSCOUT22 1 POS22 POS23 ...
Page 160
... The waveforms are edge aligned in the ramp mode Figure 16-38. PSC Run Synchronization PRUN0 PARUN0 PRUN1 PARUN1 PRUN2 PARUN2 If the PSCm has its PARUNn bit set, then it can start at the same time than PSCn-1. AT90PWM216/316 160 SY0In Run PSC0 PSC0 SY0Out SY1In Run PSC1 PSC1 ...
Page 161
... PCLKSELn bit in PSC n Configuration register (PCNFn) is used to select the clock source. PPREn1/0 bits in PSC n Control Register (PCTLn) are used to select the divide factor of the clock. 7710E–AVR–08/10 1 PLL CK 0 I/O PCLKSELn AT90PWM216/316 See “PSC 0 Control Register – PCTL0” PRESCALER PPREn1/0 CLK PSCn 161 ...
Page 162
... PSCn EC (End of Cycle): When enabled and when a match with OCRnRB occurs • PSCn CAPT (Capture Event): When enabled and one of the two following events occurs : retrigger, capture of the PSC counter or Synchro Error. See PSCn Interrupt Mask Register 16.24.2 PSC Interrupt Vectors in AT90PWM216/316 Table 16-10. PSC Interrupt Vectors Vector No. - ...
Page 163
... Description Send signal on match with OCRnRA (during counting down of PSC). The 0 min value of OCRnRA must be 1. Send signal on match with OCRnRA (during counting up of PSC). The 1 min value of OCRnRA must synchronization signal 1 no synchronization signal AT90PWM216/316 POEN0B - POEN0A R/W R/W R/W ...
Page 164
... Output Compare RA Register – OCRnRAH and OCRnRAL Bit Read/Write Initial Value 16.25.6 Output Compare SB Register – OCRnSBH and OCRnSBL Bit Read/Write Initial Value 16.25.7 Output Compare RB Register – OCRnRBH and OCRnRBL Bit Read/Write Initial Value Note : according to PSC number. AT90PWM216/316 164 – – – – OCRnSA[7: ...
Page 165
... PFIFTY0 PALOCK0 PLOCK0 PMODE01 R/W R/W R/W R PFIFTY1 PLOCK1 PMODE11 PALOCK1 R/W R/W R/W R PFIFTY2 PALOCK2 PLOCK2 PMODE21 R/W R/W R/W R AT90PWM216/316 PMODE00 POP0 PCLKSEL0 - R/W R/W R/W R PMODE10 POP1 PCLKSEL1 - R/W R/W R/W R PMODE20 POP2 PCLKSEL2 POME2 R/W R/W R/W ...
Page 166
... Table 16-14. PSC 0 Prescaler Selection PPRE01 • Bit 5 – PBFM0 : Balance Flank Width Modulation When this bit is clear, Flank Width Modulation operates on On-Time 1 only. When this bit is set, Flank Width Modulation operates on On-Time 0 and On-Time 1. AT90PWM216/316 166 PMODEn0 Description 0 One Ramp Mode 1 Two Ramp Mode 0 ...
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... PPRE11 PPRE10 PBFM1 PAOC1B R/W R/W R/W R PPRE10 Description 0 No divider on PSC input clock 1 Divide the PSC input clock Divide the PSC input clock Divide the PSC clock by 256 AT90PWM216/316 PAOC1A PARUN1 PCCYC1 PRUN1 R/W R/W R/W R PCTL1 167 ...
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... PSCOUT23 outputs. See Section “PSC Clock Sources”, page 161. • Bit 3 – PAOC2A : PSC 2 Asynchronous Output Control A When this bit is set, Fault input selected to block A can act directly to PSCOUT20 and PSCOUT22 outputs. See Section “PSC Clock Sources”, page 161. AT90PWM216/316 168 7 6 ...
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... PCAEnA PISELnA PELEVnA PFLTEnA R/W R/W R/W R PCAEnB PISELnB PELEVnB PFLTEnB R/W R/W R/W R AT90PWM216/316 PRFMnA3 PRFMnA2 PRFMnA1 PRFMnA0 R/W R/W R/W R PRFMnB3 PRFMnB2 PRFMnB1 PRFMnB0 R/W R/W R/W R PFRCnA PFRCnB 169 ...
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... PSC 0 Input Capture Register – PICR0H and PICR0L Bit Read/Write Initial Value AT90PWM216/316 170 Description No action, PSC Input is ignored PSC Input Mode 1: Stop signal, Jump to Opposite Dead-Time and Wait PSC Input Mode 2: Stop signal, Execute Opposite Dead-Time and Wait PSC Input Mode 3: Stop signal, Execute Opposite while Fault active PSC Input Mode 4: Deactivate outputs without changing timing ...
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... This bit gives the state of the PSCOUT20 (and/or PSCOUT22) during ramp 3 7710E–AVR–08/ PCST1 – – – PICR1[7: PCST2 – – – PICR2[7: POMV2B3 POMV2B2 POMV2B1 POMV2B0 R/W R/W R/W R AT90PWM216/316 PICR1[11: PICR2[11: POMV2A3 POMV2A2 POMV2A1 POMV2A0 R/W R/W R/W R PICR1H PICR1L PICR2H PICR2L POM2 171 ...
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... When this bit is set, an external event which can generates a capture from Retrigger/Fault block A generates also an interrupt. • Bit 0 – PEOPEn : PSC n End Of Cycle Interrupt Enable When this bit is set, an interrupt is generated when PSC reaches the end of the whole cycle. 16.26.5 PSC0 Interrupt Flag Register – PIFR0 Bit Read/Write Initial Value AT90PWM216/316 172 PSEIE0 ...
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... Must be cleared by software by writing a one to its location. This bit can be read even if the corresponding interrupt is not enabled (PEVEnA bit = 0). 7710E–AVR–08/ POAC1B POAC1A PSEI1 PEV1B R R R/W R POAC2B POAC2A PSEI2 PEV2B R R R/W R AT90PWM216/316 PEV1A PRN11 PRN10 PEOP1 R R PEV2A PRN21 PRN20 PEOP2 R R PIFR1 PIFR2 ...
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... Bit 0 – PEOPn: End Of PSC n Interrupt This bit is set by hardware when PSC n achieves its whole cycle. Must be cleared by software by writing a one to its location. AT90PWM216/316 174 PRNn0 Description 0 The last event which has generated an interrupt occured during ramp 1 1 The last event which has generated an interrupt occured during ramp 2 ...
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... Serial Peripheral Interface – SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the AT90PWM216/316 and peripheral devices or between several AVR devices. The AT90PWM216/316 SPI includes the following features: 17.1 Features • Full-duplex, Three-wire Synchronous Data Transfer • ...
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... SPI Data Register before the next character has been completely shifted in. Oth- erwise, the first byte is lost. In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the frequency of the SPI clock should never exceed f AT90PWM216/316 176 SHIFT ENABLE /4 ...
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... SPI Pin Overrides Direction, Master SPI User Defined Input User Defined User Defined 1. See “Alternate Functions of Port B” on page 67 direction of the user defined SPI pins. AT90PWM216/316 “Alternate Port Direction, Slave SPI Input User Defined Input Input for a detailed description of how to define the 177 ...
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... Wait for transmission complete */ while(!(SPSR & (1<<SPIF))) } Note: The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. AT90PWM216/316 178 (1) r17,(1<<DD_MOSI)|(1<<DD_SCK) DDR_SPI,r17 r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0) ...
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... Set MISO output, all others input */ DDR_SPI = (1<<DD_MISO); /* Enable SPI */ SPCR = (1<<SPE); /* Wait for reception complete */ while(!(SPSR & (1<<SPIF))) ; /* Return data register */ return SPDR; 1. The example code assumes that the part specific header file is included. AT90PWM216/316 179 ...
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... On 24 pins package, SPIPS has the following action: – When the SPIPS bit is written to zero, the SPI signals are directed on alternate SPI – When the SPIPS bit is written to one,the SPI signals are directed on pins Note that programming port are always located on alternate SPI port. AT90PWM216/316 180 7 6 ...
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... Figure 17-3 and Figure 17-4 CPOL Functionality CPOL Leading Edge 0 Rising 1 Falling Figure 17-3 CPHA Functionality CPHA Leading Edge 0 Sample 1 Setup AT90PWM216/316 CPOL CPHA SPR1 SPR0 R/W R/W R/W R for an example. The CPOL functionality is sum- Trailing Edge Falling Rising and Figure 17-4 for an example ...
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... SPI Data Register. • Bit 5..1 – Res: Reserved Bits These bits are reserved bits in the AT90PWM216/316 and will always read as zero. • Bit 0 – SPI2X: Double SPI Speed Bit When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see clock periods ...
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... Sample (Falling) Setup (Falling) SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB Bit 6 LSB first (DORD = 1) LSB Bit 1 AT90PWM216/316 SPD3 SPD2 SPD1 R/W R/W R/W R Trailing eDge Setup (Falling) Sample (Falling) ...
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... Figure 17-4. SPI Transfer Format with CPHA = 1 AT90PWM216/316 184 SCK (CPOL = 0) mode 1 SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB Bit 6 LSB first (DORD = 1) LSB Bit 1 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 2 Bit 3 Bit 4 ...
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... Bit ordering configuration (MSB or LSB first) – Sleep mode exit under reception of EUSART frame 18.2 Overview A simplified block diagram of the USART Transmitter is shown in I/O Registers and I/O pins are shown in bold. 7710E–AVR–08/10 AT90PWM216/316 Figure 18-1. CPU accessible 185 ...
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... The recovery units are used for asynchronous data reception. In addition to the recovery units, the Receiver includes a Parity Checker, Control logic, a Shift Register and a two level receive buffer (UDR). The Receiver supports the same frame formats as the Transmitter, and can detect Frame Error, Data OverRun and Parity Errors. AT90PWM216/316 186 (1) UBRR[H:L] ...
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... DDR_XCKn Transmitter clock (Internal Signal). Receiver base clock (Internal Signal). Input from XCK pin (internal Signal). Used for synchronous slave Clock output to XCK pin (Internal Signal). Used for synchronous master operation. clk System I/O Clock frequency. io AT90PWM216/316 clk Edge Detector UCPOLn Figure 18-2 ...
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... Transmitter and Receiver. This process intro- duces a two CPU clock period delay and therefore the maximum external XCK clock frequency is limited by the following equation: AT90PWM216/316 188 contains equations for calculating the baud rate (in bits per second) and for calculat- ...
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... It is therefore recommended io UCPOLn = 1 XCKn RxDn / TxDn UCPOLn = 0 XCKn RxDn / TxDn Figure 18-3 shows, when UCPOL is zero the data will be changed at illustrates the possible combinations of the frame formats. Bits inside brackets are AT90PWM216/316 Sample Sample 189 ...
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... The initialization process normally consists of setting the baud rate, setting frame format and enabling the Transmitter or the Receiver depending on the usage. For interrupt driven USART operation, the Global Interrupt Flag should be cleared (and inter- rupts globally disabled) when doing the initialization. AT90PWM216/316 190 FRAME (IDLE) ...
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... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. AT90PWM216/316 191 ...
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... Note: The function simply waits for the transmit buffer to be empty by checking the UDRE flag, before loading it with new data to be transmitted. If the Data Register Empty interrupt is utilized, the interrupt routine writes the data into the buffer. AT90PWM216/316 192 (1) ( The example code assumes that the part specific header file is included. ...
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... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. AT90PWM216/316 193 ...
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... Receive Shift Register, the contents of the Shift Register will be moved into the receive buffer. The receive buffer can then be read by reading the UDR I/O location. AT90PWM216/316 194 7710E–AVR–08/10 ...
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... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. AT90PWM216/316 195 ...
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... UCSRA; resh = UCSRB; resl = UDR error, return - status & (1<<FE0)|(1<<DOR0)|(1<<UPE0 Filter the 9th bit, then return */ resh = (resh >> 1) & 0x01; return ((resh << resl); } Note: AT90PWM216/316 196 (1) r18, UCSRA r17, HIGH(-1) r16, LOW(-1) r17 (1) ; return -1; ...
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... CH1 and CH2, CH3 is lost. When a Data OverRun condition is detected, the OverRun error is memorized. When the two characters CH1 and CH2 are read from the receive buffer, the DOR bit is set (and not before) and RxC remains set to warn the application about the overrun error. 7710E–AVR–08/10 AT90PWM216/316 197 ...
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... Unread data will be lost. If the buffer has to be flushed during normal operation, due to for instance an error condition, read the UDR I/O location until the RXC flag is cleared. The following code example shows how to flush the receive buffer. AT90PWM216/316 198 CH1 CH2 ...
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... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. RxDn IDLE Sample (U2Xn = Sample (U2Xn = 1) AT90PWM216/316 START Figure 18-6 ...
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... Frame Error (FE) flag will be set. A new high to low transition indicating the start bit of a new frame can come right after the last of the bits used for majority voting. For Normal Speed mode, the first low level sample can be at AT90PWM216/316 200 RxDn ...