AT89LP828-20JU Atmel, AT89LP828-20JU Datasheet - Page 37

• Manufacturer Part Number: AT89LP828-20JU
• Description: MCU 8051 8K FLASH SPI 32PLCC
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP828-20JU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-PLCC
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: 2-Wire, SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 30
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89ISP
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

10.1.2
10.1.3
3654A–MICRO–8/09
Input-only Mode
Open-drain Output
The input only port configuration is shown in
input includes a Schmitt-triggered input for improved input noise rejection. The input circuitry of
P3.2, P3.3, P3.6, P4.0 and P4.1 is not disabled during Power-down (see
fore these pins should not be left floating during Power-down when configured in this mode.
Figure 10-2. Input Only
Figure 10-3. Input Circuit for P3.2, P3.3 and P3.6
The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor
of the port pin when the port latch contains a logic “0”. To be used as a logic output, a port con-
figured in this manner must have an external pull-up, typically a resistor tied to V
down for this mode is the same as for the quasi-bidirectional mode. The open-drain port configu-
ration is shown in
Power-down (see
down when configured in this mode.
Figure 10-4. Open-drain Output
From Port
Register
Figure
Figure
Input
Data
Input
Data
10-3) and therefore these pins should not be left floating during Power-
10-4. The input circuitry of P3.2, P3.3 and P3.6 is not disabled during
PWD
Input
Data
Figure
PWD
10-2. The output drivers are tristated. The
AT89LP428/828
Port
Pin
Port
Pin
Figure
Port
Pin
10-3) and there-
CC
. The pull-
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