AT89LP828-20JU Atmel, AT89LP828-20JU Datasheet - Page 16

• Manufacturer Part Number: AT89LP828-20JU
• Description: MCU 8051 8K FLASH SPI 32PLCC
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP828-20JU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-PLCC
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: 2-Wire, SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 30
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89ISP
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

5. Enhanced CPU
16
AT89LP428/828
The AT89LP428/828 uses an enhanced 8051 CPU that runs at 6 to 12 times the speed of stan-
dard 8051 devices (or 3 to 6 times the speed of X2 8051 devices). The increase in performance
is due to two factors. First, the CPU fetches one instruction byte from the code memory every
clock cycle. Second, the CPU uses a simple two-stage pipeline to fetch and execute instructions
in parallel. This basic pipelining concept allows the CPU to obtain up to 1 MIPS per MHz. A sim-
ple example is shown in
Figure 5-1.
The MCS-51 instruction set allows for instructions of variable length from 1 to 3 bytes. In a sin-
gle-clock-per-byte-fetch system this means each instruction takes at least as many clocks as it
has bytes to execute. The majority of instructions in the AT89LP428/828 follow this rule: the
instruction execution time in clock cycles equals the number of bytes per instruction with a
few exceptions. Branches and Calls require an additional cycle to compute the target address
and some other complex instructions require multiple cycles. See
page 107
examples of 1- and 2-byte instructions.
Figure 5-2.
Register Operand Fetch
ALU Operation Execute
(n+1)
Fetch Next Instruction
(n+2)
Total Execution Time
for more detailed information on individual instructions.
Result Write Back
System Clock
n
th
th
th
Parallel Instruction Fetches and Executions
Single-cycle ALU Operation (Example: INC R0)
Instruction
Instruction
Instruction
System Clock
Figure
5-1.
Fetch
T
n
T
1
Execute
Fetch
T
n+1
T
2
“Instruction Set Summary” on
Figures 5-2 and 5-3
Execute
Fetch
T
n+2
T
3
3654A–MICRO–8/09
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